3D Semiconductor Device Vertical Stacking for Storage Density
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Solution Overview
Problem
The increasing demand for smaller, lower power consumption, and higher performance electronic devices has led to challenges in reducing the size of semiconductor devices while maintaining data storage capacity, particularly as the costs and complexities of manufacturing two-dimensional semiconductor devices with reduced metal line widths have escalated.
Innovation Solution
A semiconductor device with a three-dimensional structure is proposed, featuring a bit line extending in a vertical direction, active layers extending horizontally and contacting the bit line, word lines disposed on the top or bottom surfaces of the active layers, capacitors contacting the active layers, and a contact formed in the uppermost active layer to facilitate electrical connection or separation using a word line as a control line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor devices use reduced metal line width to increase data storage capacity, then storage capacity per area is improved, but manufacturing cost and complexity increase exponentially
Solution Approach 1:
The patent transitions from two-dimensional planar structures to three-dimensional vertical structures by stacking multiple active layers, bit lines, and word lines in the third dimension (depth direction). This allows multiple memory cells to be stacked vertically, increasing storage capacity without requiring further reduction of metal line widths, thereby avoiding the exponential increase in manufacturing complexity associated with ultra-fine lithography.
2Area of stationary object
If two-dimensional semiconductor devices reduce metal line width to reduce device size, then device footprint is reduced, but manufacturing cost increases exponentially
Solution Approach 1:
The patent employs vertical stacking of active layers, bit lines, and word lines to build memory capacity in the third dimension. This three-dimensional architecture reduces the lateral footprint of the device while maintaining or increasing storage capacity, and avoids the need for extremely narrow metal lines that would require complex and expensive manufacturing processes.
3Quantity of substance
If three-dimensional structure is implemented with stacked active layers and bit lines, then storage capacity and size are improved, but contact formation complexity increases
Solution Approach 1:
The patent divides the three-dimensional structure into discrete stacked active layers (first, second, third active layers) with corresponding bit lines and word lines. Contacts are formed selectively in specific active layers (e.g., first and third active layers) to connect to bit lines, while the second active layer serves as a separator. This segmentation simplifies contact formation by concentrating contacts in specific layers rather than requiring complex interlayer connections throughout the stack.
Solution Approach 2:
The bit lines extend through multiple active layers and serve multiple functions: they act as electrical connections for memory cells in different layers, serve as control lines for selecting specific memory cells, and provide structural support for the stacked architecture. This multi-functionality reduces the need for separate dedicated contact structures for each layer.
Data Source
AI summary
A semiconductor device may include a bit line extending in a third direction, a plurality of active layers extending in a first direction and contacting the bit line, a plurality of word lines extending in a second direction and each disposed at an top surface or bottom surface of each of the plurality of active layers, a plurality of capacitors contacting the plurality of active layers, and a contact formed in at least one active layer disposed at the uppermost part of the bit line, among the plurality of active layers. The bit line and the contact may be electrically connected or separated by using, as a control line, a word line disposed in the top surface or bottom surface of the at least one active layer, among the plurality of word lines.