Semiconductor Device Layout and Gate Dielectric Tuning for WPE
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Solution Overview
Problem
The reduction in size and gap of transistors in semiconductor devices leads to increased dispersion of electrical characteristics due to the well proximity effect (WPE), which is a challenge for high integration.
Innovation Solution
The semiconductor device incorporates specific configurations of P-wells, N-wells, and N-type active regions with varying distances and thicknesses of P-gate dielectric layers and P-work function metal layers to control the threshold voltage and reduce dispersion of electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size and gap of transistors are reduced for high integration, then the integration density is improved, but the dispersion of electrical characteristics increases due to well proximity effect
Solution Approach 1:
The patent applies local quality by differentiating the gate dielectric layer structure between transistors adjacent to wells and those not adjacent to wells. Specifically, transistors adjacent to wells receive an additional first gate dielectric layer with a first threshold voltage, while other transistors receive only a second gate dielectric layer with a second threshold voltage. This localized structural differentiation compensates for the well proximity effect in specific regions, thereby reducing electrical characteristic dispersion across the entire transistor array while maintaining high integration density.
2Area of stationary object
If transistors are placed closer together to increase integration, then the device area is reduced, but the well proximity effect causes greater variation in electrical characteristics
Solution Approach 1:
The patent employs parameter changes by modifying the threshold voltage parameter of the gate dielectric layer in specific transistor regions. By introducing a first gate dielectric layer with a first threshold voltage for transistors adjacent to wells, and a second gate dielectric layer with a second threshold voltage for other transistors, the patent adjusts electrical parameters to compensate for well proximity effects. This enables closer transistor placement for reduced device area while maintaining electrical characteristics consistency through parameter differentiation.
Data Source
AI summary
A semiconductor device includes an N-well between first and second P-wells. N-type active regions including first and second N-type active regions are disposed in the N-well. A shortest distance between a boundary of the second P-well and the N-well and the second N-type active region is larger than a shortest distance between a boundary of the first P-well and the N-well and the first N-type active region. A first P-gate dielectric layer including a first modulation layer is provided on the first N-type active region. The first modulation layer includes a first intermediate modulation layer between lower and upper modulation layers. A second P-gate dielectric layer including a second modulation layer is provided on the second N-type active region. The second modulation layer includes a second intermediate modulation layer between the lower and upper modulation layers. The first intermediate modulation layer is thicker than the second intermediate modulation layer.