Semiconductor Device Parallel Metal Wiring Inductance Reduction
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Solution Overview
Problem
High inductance within power semiconductor modules leads to over-voltage during high-speed switching, causing potential breakdown and increased switching losses, limiting the ability to perform high-speed switching.
Innovation Solution
The semiconductor device incorporates a configuration with parallel metal wiring layers to reduce inductance, featuring a metal substrate with overlapping N-type and P-type metal wiring layers, which are connected to semiconductor chips via metal plugs and solder, allowing for surface contact and improved heat dissipation using copper materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional metal wiring configuration is used, then device complexity is reduced, but inductance becomes large causing over-voltage and breakdown
Solution Approach 1:
The patent transitions from planar metal wiring to a three-dimensional stacked configuration with multiple metal wiring layers (first, second, and third metal wiring layers) positioned at different heights. This vertical dimensionality reduction allows current paths to be shortened and inductance to be reduced from tens of nH to 10 nH or less, preventing over-voltage and module breakdown during high-speed switching.
Solution Approach 2:
The patent implements a nested structure where the second metal wiring layer is disposed over the first metal wiring layer, and the third metal wiring layer is disposed over portions of the first and second metal wiring layers. This nested arrangement creates compact current loops and reduces the area enclosed by current paths, thereby minimizing inductance while maintaining a compact module structure.
2Speed
If high-speed switching is performed with large inductance, then switching speed is improved, but over-voltage is generated causing breakdown
Solution Approach 1:
The patent changes the electrical parameters of the wiring system by reducing inductance from conventional values (tens of nH) to 10 nH or less through the multi-layer metal wiring configuration. This parameter change enables high-speed switching operation without generating excessive over-voltage, as the reduced inductance limits the voltage spike (V = L × di/dt) during rapid current changes.
3Loss of energy
If inductance is reduced for high-speed switching, then switching losses are reduced, but device complexity increases
Solution Approach 1:
The patent merges multiple functions into the metal wiring layers: they serve as both electrical connection paths and inductance-reduction structures. The first, second, and third metal wiring layers are electrically connected to terminals and semiconductor chips while simultaneously forming compact current loops that reduce inductance. This merging eliminates the need for separate inductance-reduction components, reducing overall device complexity despite the multi-layer configuration.
Data Source
AI summary
A semiconductor device includes a first and a second metal layer, the second provided on a same plane as the first layer, and first second and third terminals. A first metal wiring layer is electrically connected to the first terminal. A second metal wiring layer is electrically connected to the second terminal and the second metal layer and disposed over the first metal wiring layer. A third metal wiring layer is electrically connected to the third terminal and the first metal layer. A first semiconductor chip is provided between the first metal wiring layer and the first metal layer. A second semiconductor chip is provided between the third metal wiring layer and the second metal layer. The first chip has electrodes connected to the first metal wiring layer and the first metal layer. The second chip has electrodes connected to the third metal wiring layer and the second metal layer.