Semiconductor Device With Diagonal Transistor Chips and V-Shaped Gate Fingers
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Solution Overview
Problem
Conventional semiconductor devices face challenges in increasing output without enlarging package size, which leads to deterioration in characteristics and reliability due to heat concentration and phase differences in transistor chip arrangements.
Innovation Solution
A semiconductor device with diagonally arranged transistor chips and a V-shaped arrangement of gate fingers to optimize chip placement and heat dissipation, maintaining package size while enhancing output and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the gate width is increased to improve output, then the output increases, but the package size increases
Solution Approach 1:
The gate fingers are arranged in a V-shape configuration instead of a straight line, utilizing two-dimensional spatial arrangement to increase the effective gate width within the same package footprint. This dimensional change allows the gate width to expand in a radial pattern from the gate pad, achieving higher output without increasing package lateral dimensions.
Solution Approach 2:
The gate electrode is divided into multiple gate fingers arranged in a V-shape pattern, with each finger contributing to the total gate width. This segmentation allows the gate width to be increased by adding more fingers or extending finger length without requiring a proportional increase in package size, as the V-shape arrangement packs the fingers more efficiently in space.
2Power
If the finger spacing is narrowed to increase the number of fingers, then the gate width increases, but heat concentration occurs and reliability deteriorates
Solution Approach 1:
The V-shape arrangement distributes heat-generating gate fingers in a radial pattern rather than a linear sequence, spreading the heat generation area across a larger effective area. This dimensional distribution reduces localized heat concentration at any single point while maintaining high total gate width, thereby improving heat dissipation and reliability.
Solution Approach 2:
The gate fingers are arranged with varying spacing and orientations in the V-shape configuration, creating different local thermal environments. This allows regions with higher heat generation to have slightly larger spacing for better heat dissipation, while maintaining tight spacing in regions where heat load is lower, optimizing both gate width and thermal management.
3Power
If the gate finger length is increased to increase gate width, then the gate width increases, but the gain decreases
Solution Approach 1:
Instead of using a few long gate fingers that reduce gain, the total gate width is achieved by segmenting it into multiple shorter fingers arranged in a V-shape. Each finger maintains an optimal length for high gain performance, while the collective arrangement of multiple fingers achieves the required total gate width for high output.
Solution Approach 2:
The V-shape arrangement allows multiple gate fingers of optimal (shorter) length to be packed into an effective gate width that would otherwise require much longer fingers in a linear arrangement. By utilizing the radial/V-shaped spatial configuration, the patent achieves equivalent gate width with shorter individual fingers, preserving gain characteristics.
4Area of stationary object
If chips are arranged before or after each other to reduce package size, then the package size decreases, but only ends of chips can overlap which limits further size reduction
Solution Approach 1:
The transistor chips are arranged diagonally with their long sides at 45 degrees to the input/output direction, utilizing two-dimensional diagonal spacing to maximize chip density. This diagonal arrangement, combined with the V-shaped gate finger configuration, allows chips to be packed more efficiently than linear or simple stacked arrangements, achieving higher chip count per unit area without wire contact issues.
Data Source
AI summary
A semiconductor device includes: a package; an input matching circuit and an output matching circuit in the package; and transistor chips between the input matching circuit and the output matching circuit in the package. Each transistor chip includes a semiconductor substrate having long sides and short sides that are shorter than the long sides, and a gate electrode, a drain electrode and a source electrode on the semiconductor substrate. The gate electrode has gate fingers arranged along the long sides of the semiconductor substrate and a gate pad commonly connected to the gate fingers and connected to the input matching circuit via a first wire. The drain electrode is connected to the output matching circuit via a second wire. The long sides of the semiconductor substrates of the transistor chips are oblique with respect to an input/output direction extending from the input matching circuit to the output matching circuit.