Semiconductor Chip Pads with Diagonal Wire Bonding for Miniaturization
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Solution Overview
Problem
The size of semiconductor chip pads is limited by their size, making it difficult to reduce the overall size of semiconductor chips due to issues with wire bonding equipment and bonding strength, which hinders the increase in chip integration density.
Innovation Solution
The semiconductor device features chip pads with different orientations and sizes, where first chip pads are connected to straight wires and second chip pads are connected to diagonal wires, allowing for a reduction in pad width without compromising bonding strength, enabling smaller chip sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If chip pads are reduced in size, then chip area is reduced, but bonding strength with wire is reduced
Solution Approach 1:
The patent applies asymmetry by introducing diagonal wires at 45-degree angles relative to the chip edges, creating asymmetric bonding configurations. This asymmetric wire arrangement allows for reduced pad area while maintaining bonding strength through optimized stress distribution patterns that differ from conventional symmetric parallel wires.
Solution Approach 2:
The patent changes the geometric parameters of wire bonding by introducing diagonal orientations at 45 degrees instead of conventional parallel arrangements. This parameter change in wire angle enables reduced pad area while maintaining adequate bonding strength through altered stress distribution characteristics.
2Productivity
If number of chip pads is increased, then integration density is improved, but chip size is increased
Solution Approach 1:
The patent transitions from two-dimensional parallel wire arrangements to a three-dimensional diagonal configuration by introducing wires at 45-degree angles. This dimensional change in wire orientation enables more efficient space utilization, allowing increased integration density without proportional increases in chip area.
Solution Approach 2:
By implementing asymmetric diagonal wire patterns, the patent enables more compact pad arrangements that support higher integration density within reduced chip footprints, breaking the conventional scaling relationship between pad count and chip area.
Data Source
AI summary
Disclosed are a semiconductor device and a stacked semiconductor package. The semiconductor device may include a semiconductor chip and a plurality of chip pads disposed on the semiconductor chip in a second horizontal direction perpendicular to a first horizontal direction. The plurality of chip pads may include: a first chip pad connected to a wire extending in the first horizontal direction, when seen from the top; and a second chip pad connected to a diagonal wire extending in a direction at an angle to the first and second horizontal directions, when seen from the top. The width of the first chip pad in the second horizontal direction may be smaller than the width of the second chip pad in the second horizontal direction.