Semiconductor Dicing Structures for Crack Prevention
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Solution Overview
Problem
Low-k and ultra-low dielectric constant materials in semiconductor technology face challenges with poor mechanical properties, leading to crack propagation and delamination issues during processing and operation, which affect product yield and reliability.
Innovation Solution
The introduction of a dicing structure with specific metal features and alignment marks in the semiconductor substrate, where metal lines are strategically placed above and below the alignment marks to enhance mechanical strength and minimize misalignment errors during dicing, while avoiding interference with alignment detection units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low-k and ultra-low dielectric constant materials are used to minimize interconnect parasitic capacitances, then electrical performance is improved, but mechanical properties deteriorate leading to crack propagation and delamination
Solution Approach 1:
The patent introduces crack stop structures that segment the continuous low-k dielectric layer into isolated regions. These crack stop structures are formed by removing portions of the low-k dielectric material, creating physical barriers that prevent crack propagation across the entire wafer while maintaining the electrical benefits of low-k materials in the remaining regions.
Solution Approach 2:
The patent introduces intermediary structures (crack stop structures and support structures) that mediate between the weak low-k dielectric material and the mechanical stresses during processing. These intermediary structures provide mechanical support and stress relief, preventing delamination and crack propagation while allowing the low-k material to maintain its electrical performance.
2Ease of operation
If dicing streets are created to separate chips on a semiconductor wafer, then chip separation is achieved, but mechanical strength is reduced leading to increased susceptibility to cracking and delamination
Solution Approach 1:
The patent forms crack stop structures and support structures in the dicing streets before the actual dicing process. These structures are prepared in advance to provide mechanical reinforcement during subsequent processing steps including dicing, preventing cracks from initiating or propagating during chip separation.
Solution Approach 2:
The patent applies different structural qualities to different regions of the wafer. In the dicing street regions, crack stop structures and support structures are formed to provide enhanced mechanical strength, while the chip regions maintain their normal structure for electrical functionality. This localized reinforcement addresses the mechanical weakness at dicing streets without affecting chip performance.
3Strength
If metal features are added to dicing streets to enhance mechanical strength, then structural integrity is improved, but alignment detection may be interfered with during dicing
Solution Approach 1:
The patent carefully positions metal features (crack stop structures and support structures) in specific locations within the dicing streets, away from the alignment marks. This localized placement ensures that the metal features provide mechanical reinforcement without interfering with the optical detection of alignment marks during the dicing process.
Solution Approach 2:
The patent positions metal features in the vertical dimension (cross-sectional view) rather than directly over the alignment marks in the horizontal plane. The metal features are disposed at different heights and positions in the dicing street structure, allowing them to provide mechanical support while leaving the alignment mark detection path clear.
Data Source
AI summary
Dicing structures for semiconductor substrates and methods of fabrication thereof are described. In one embodiment, a semiconductor wafer includes a first chip disposed in a substrate, a second chip disposed adjacent the first chip and disposed in the substrate, and a dicing street disposed between the first and the second chip. A first and a second metal level are disposed over the dicing street, wherein the second metal level is disposed above the first metal level. A first alignment mark is disposed in the first metal level above a first portion of the dicing street, and first metal features disposed in the second metal level above the first portion of the dicing street.