Semiconductor Dicing via Segmented Backside Metallization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor fabrication methods face challenges with the thick back side solder metal, leading to defects such as chipping and die cracks during dicing, especially when the thickness exceeds 1 μm, which hinders the adoption of modern dicing methods like plasma and laser dicing.
Innovation Solution
A method involving a thin contact layer over a substrate with a structured solder layer, where the contact layer is exposed in the kerf regions, allowing for dicing through the contact layer rather than the thicker solder layer, thereby reducing defectivity and enabling the use of advanced dicing techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick back side solder metal layer is used, then the mechanical strength and reliability of the semiconductor device is improved, but the dicing process generates defects such as chipping and die cracks
Solution Approach 1:
The back side metallization is segmented into two distinct layers: a thin contact layer (50-200 nm) that extends to the kerf region and a thicker solder layer (1-10 μm) that is confined to the device region. This segmentation allows the dicing blade to cut through only the thin contact layer without damaging the thicker solder layer, thereby eliminating dicing-induced defects while preserving the mechanical strength provided by the solder layer.
Solution Approach 2:
The contact layer is designed with non-uniform local properties: it has a greater width in the kerf region compared to the device region, and its thickness is optimized to be minimal where dicing occurs. This local quality variation ensures that the contact layer facilitates clean dicing separation in the kerf region while the solder layer provides robust mechanical support in the device region.
2Manufacturing precision
If a thin contact layer is used instead of thick solder layer, then the dicing process quality is improved, but the electrical conductivity and mechanical support may be compromised
Solution Approach 1:
The metallization structure is segmented into functionally distinct layers: the thin contact layer optimized for dicing quality and the thick solder layer optimized for electrical conductivity and mechanical support. The contact layer's thin profile (50-200 nm) enables defect-free dicing, while the solder layer's substantial thickness (1-10 μm) ensures adequate electrical and mechanical performance.
Solution Approach 2:
The contact layer and solder layer are merged into a unified back side metallization structure where the contact layer serves as an intermediate transition between the substrate and the solder layer. This merging allows the thin contact layer to facilitate clean dicing while the thick solder layer provides the necessary electrical and mechanical properties, achieving both dicing quality and reliability simultaneously.
Data Source
AI summary
In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.