Semiconductor Dicing Method With Trench Etching
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Solution Overview
Problem
Current dicing methods for semiconductor chips are limited in reducing the thickness and width of sawing streets, leading to larger chip sizes and potential edge chipping during the dicing process.
Innovation Solution
A dicing method involving a substrate with integrated components, where a handling wafer is attached to the main surface, the substrate is thinned, and trenches are formed in a single etching step from the main surface to the rear surface, with optional through-substrate vias and bumps, allowing for reduced scribe line width and smooth chip edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional sawing methods are used for dicing, then the process is simple and straightforward, but the sawing street width is large (typically about 60 μm) and chip edges may break
Solution Approach 1:
The dicing process is divided into two distinct stages: first forming trenches to define separation regions, then performing the actual cutting operation. This segmentation allows each stage to be optimized independently - trenches can be made very narrow (20 μm or smaller) while the cutting tool operates in controlled spaces between trenches, reducing edge stress and breakage risk
Solution Approach 2:
Trenches are formed in advance before the actual dicing operation. These pre-formed trenches serve as guides and stress-relief features that prevent chip edge breakage during subsequent cutting. The masking layer is also structured beforehand to define precise trench locations, enabling better control over final chip dimensions
2Productivity
If trench dicing is used to reduce sawing street width to 20 μm or smaller, then yield per wafer increases, but the process complexity increases with masking and etching steps
Solution Approach 1:
The trench structure serves multiple functions simultaneously: it defines the separation boundary between chips, acts as a stress-relief feature to prevent breakage, and provides a precise guide for the subsequent dicing operation. The masking layer also serves dual purposes of defining trench locations and protecting chip areas during etching
Solution Approach 2:
The mechanical sawing process is replaced with a combination of lithographic patterning and chemical etching to form trenches. This substitution enables much narrower features (20 μm or smaller) to be achieved with higher precision and better edge quality compared to direct mechanical cutting
3Productivity
If laser dicing is used, then no physical contact is made with chips, but productivity is lower compared to trench dicing
Solution Approach 1:
The patent combines the advantages of both trench dicing and laser dicing by using trenches to define separation regions (as in trench dicing) followed by laser cutting within those defined spaces. This merging approach achieves the high productivity of laser dicing while obtaining the narrow street width and edge quality benefits of trench dicing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the production of thinner chips with reduced scribe line width, minimizing the risk of edge chipping and allowing for more efficient chip separation with smoother edges, while also enabling the formation of narrow through-substrate vias and redistribution layers.
Implementation Method 1
forming trenches penetrating the substrate and separating the chips by a single etching step
Data Source
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AI summary
The dicing method comprises the steps of providing a substrate (1) of semiconductor material, the substrate having a main surface (10), where integrated components (3) of chips (13) are arranged, and a rear surface (11) opposite the main surface, fastening a first handling wafer above the main surface, thinning the substrate at the rear surface, and forming trenches (20) penetrating the substrate and separating the chips by a single etching step after the substrate has been thinned.