Semiconductor Die Air Gap Structure for Lower Parasitic Capacitance

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Solution Overview

Problem

High integration density in semiconductor dies leads to reduced reliability due to increased capacitive coupling between conductive features, which affects performance and power consumption.

Innovation Solution

A semiconductor die structure with air gaps and a liner layer is created between conductor blocks, reducing parasitic capacitance by separating conductive features, and a method involving forming supporting backbones, conductor blocks, and air gaps with a heat treatment process to transform an energy removable layer into air gaps enclosed by a liner layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If high integration density is implemented in semiconductor dies, then functionality and capacity are improved, but reliability deteriorates due to increased capacitive coupling between conductive features

Engineering Contradiction:
Improveintegration densityVSAvoidreliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent introduces air gap structures that segment and separate adjacent conductor blocks, dividing the continuous dielectric medium into distinct regions. This segmentation reduces the capacitive coupling between conductors by inserting low-k air gaps between them, thereby maintaining high integration density while improving reliability through reduced interference.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The air gap structure acts as an intermediary layer between adjacent conductor blocks. This intermediary introduces a low-dielectric constant region that mediates the electric field interaction between conductors, reducing parasitic capacitance and signal interference while allowing the conductors to remain in close proximity for high-density integration.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Use of energy by moving object

If air gap structures are introduced to reduce parasitic capacitance, then power consumption and RC delay are decreased, but device structure becomes more complex

Engineering Contradiction:
Improvepower consumptionVSAvoiddevice structure
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent changes the dielectric parameter (k-value) by introducing air gaps with low dielectric constant between conductor blocks. This parameter change reduces the capacitive coupling coefficient, thereby decreasing power consumption and RC delay. The method achieves this through controlled formation processes that create air gaps without requiring fundamental redesign of the device architecture.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The air gap structures are formed using sacrificial materials (such as organic compounds) that are subsequently removed through thermal decomposition or other removal processes. These sacrificial materials serve as temporary structures during fabrication, enabling the creation of air gaps without permanent complex tooling or equipment, thus reducing overall device structure complexity.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach decreases power consumption and resistive-capacitive (RC) delay, improving overall device performance and increasing the yield rate of semiconductor devices.

Implementation Method 1

performing a heat treatment process to transform the energy removable layer into a plurality of air gap structures

Methodology Applied
Scientific EffectThermal decomposition: Pyrolysis

Data Source

PatentUS11764108B2Method for preparing semiconductor die structure with air gaps
Publication Date: 2023.09.19 NAN YA TECH
  • US11764108B2 patent drawing
  • US11764108B2 patent drawing
  • US11764108B2 patent drawing

AI summary

The present disclosure provides a method for preparing a semiconductor die structure with air gaps for reducing capacitive coupling between conductive features and a method for preparing the semiconductor die structure. The method includes: forming a first supporting backbone on the substrate; forming a first conductor block on the first supporting backbone; forming a second supporting backbone on the substrate; forming a second conductor block on the second supporting backbone; forming a third conductor block suspended above the substrate and connected to the first conductor block and the second conductor block; sequentially forming an energy removable layer and a capping dielectric layer over the substrate, and the energy removable layer and the capping dielectric layer separating the first conductor block, the second conductor block and the third conductor block; and performing a heat treatment process to transform the energy removable layer into a plurality of air gap structures.