Semiconductor Die Alignment Using Test Signal Switches

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Solution Overview

Problem

The challenge in semiconductor manufacturing lies in accurately aligning semiconductor dies or wafers for effective communication, as misalignment leads to defects and decreased yield in semiconductor devices.

Innovation Solution

The implementation of a semiconductor die and wafer design with test signal generators, receivers, and switch controllers that utilize pads with varying intervals for alignment testing, allowing for precise alignment and coupling by determining misalignment directions and distances through test operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If semiconductor dies or wafers are coupled without alignment testing, then the manufacturing process is simpler and faster, but the alignment precision deteriorates leading to communication failures and defects

Engineering Contradiction:
Improvealignment precisionVSAvoiddevice complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by performing alignment testing before final coupling. Test signal generators and receivers are used to detect pad positions and determine misalignment directions and distances beforehand, allowing corrective actions to be taken before the actual coupling process, thus ensuring precise alignment without compromising manufacturing efficiency

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback mechanisms where test signals are transmitted through pads and the responses are analyzed to provide information about alignment status. This feedback loop enables real-time detection of misalignment and guides adjustment processes, ensuring that coupling is performed only when proper alignment is confirmed

Inventive Principle:
Principle #23Feedback

2Productivity

If alignment testing is performed to improve coupling accuracy, then the manufacturing yield increases, but the manufacturing time and process complexity increase

Engineering Contradiction:
Improvemanufacturing yieldVSAvoidmanufacturing time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent applies partial action by performing alignment testing on selected critical pads rather than all pads, and by performing testing only when necessary based on process conditions. This selective approach maintains high yield by ensuring critical alignments are verified while minimizing the time penalty associated with comprehensive testing of every component

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

By performing alignment testing in advance before final coupling, the patent prevents defects rather than detecting them later. This preliminary verification ensures that only properly aligned dies or wafers proceed to coupling, thereby improving yield without requiring rework or rejection of marginal cases

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If pads with varying intervals are used for alignment testing, then the ability to detect misalignment improves, but the device design complexity increases

Engineering Contradiction:
Improvemisalignment detection precisionVSAvoiddevice design complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies asymmetry by using pads with varying intervals rather than uniform spacing. This asymmetric arrangement creates distinctive signal patterns that provide more information about misalignment direction and magnitude, enabling more precise measurement of alignment errors while the added design complexity is offset by the significant improvement in measurement capability

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS11348848B2Semiconductor die, semiconductor wafer, semiconductor device including the semiconductor die and method of manufacturing the semiconductor device
Publication Date: 2022.05.31 SAMSUNG ELECTRONICS CO LTD
  • US11348848B2 patent drawing
  • US11348848B2 patent drawing
  • US11348848B2 patent drawing

AI summary

A nonvolatile memory device includes a memory cell region including first pads and a peripheral circuit region including second pads. The regions comprises switches that are electrically connected with the pads, respectively, a test signal generator that generates test signals and to transmit the test signals to the switches, internal circuits that receive first signals through the pads and the switches, to perform operations based on the first signals, and to output second signals through the switches and the pads based on a result of the operations, and a switch controller that controls the switches so that the pads communicate with the test signal generator during a test operation and that the pads communicate with the internal circuits after a completion of the test operation. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.