Semiconductor Die Assembly Thermal Path Design
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Solution Overview
Problem
Semiconductor die assemblies with stacked die packages face overheating issues due to inefficient heat transfer, particularly as the density of dies increases, as heat generated by logic dies must pass through multiple thermal paths and semiconductor dies to reach the thermally conductive casing.
Innovation Solution
The semiconductor die assembly incorporates an embedded memory die partially or entirely within a substrate cavity, with a thermally conductive casing and conductive vias for improved heat transfer, reducing path resistance and enhancing thermal performance by directly conveying heat from the logic die to the casing without passing through the memory dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If multiple thermal paths are used to transfer heat from logic die to thermally conductive casing, then heat transfer efficiency is improved, but device complexity increases
Solution Approach 1:
The patent extracts the memory die from the thermal path between the logic die and the thermally conductive casing. By creating a cavity in the substrate and embedding the memory die within it, the design separates the memory component from the primary heat conduction path, allowing heat to flow directly from the logic die through the substrate to the casing without being blocked by memory dies. This resolves the contradiction by maintaining thermal efficiency while simplifying the thermal management architecture.
Solution Approach 2:
The patent transitions from a planar stacked die configuration to a three-dimensional structure with a cavity. By embedding the memory die within a cavity in the substrate rather than stacking it directly on the logic die, the design creates a spatial separation that allows thermal paths to operate independently in different dimensional spaces. This enables efficient heat transfer while accommodating multiple components without increasing overall device complexity.
2Productivity
If die density in stacked package is increased, then productivity is improved, but thermal performance deteriorates
Solution Approach 1:
The patent segments the device into distinct functional zones: a logic die region for heat generation, a substrate with embedded memory dies for data storage, and a thermally conductive casing for heat dissipation. The cavity in the substrate creates a dedicated thermal conduction channel that is separate from the memory die stack. This segmentation allows high die density in the memory region while maintaining an unobstructed thermal path from the logic die to the casing, resolving the contradiction between density and thermal performance.
Solution Approach 2:
The substrate with the embedded memory die acts as an intermediary structure that simultaneously supports high-density memory integration and provides a thermal conduction pathway. The cavity in the substrate serves as a mediator that allows thermal energy to pass through the substrate region without being blocked by memory dies, enabling both high productivity through dense packaging and maintained thermal performance.
3Ease of manufacture
If logic die thickness is increased for better manufacturability, then ease of manufacture is improved, but thermal path resistance increases
Solution Approach 1:
The patent applies local quality by creating a cavity in the substrate at the specific location where thermal conduction is needed. This localized structural modification allows the substrate to have different properties in different regions: the cavity region provides low thermal resistance for heat flow from the logic die, while other regions of the substrate can maintain standard thickness and properties for structural support and manufacturability. This resolves the contradiction by optimizing the thermal path locally without compromising overall manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration provides faster and more efficient heat transfer away from the logic die, reducing overheating and improving thermal performance compared to traditional approaches by minimizing thermal path resistance and allowing for a thicker, more manufacturable logic die.
Implementation Method 1
a first face of a logic die coupled to the thermally conductive casing to form a thermal path that transfers heat away from the logic die to the thermally conductive casing
Implementation Method 2
conductive vias for improved heat transfer, reducing path resistance and enhancing thermal performance
Data Source
AI summary
Semiconductor die assemblies and methods of forming the same are described herein. As an example, a semiconductor die assembly may include a thermally conductive casing, a first face of a logic die coupled to the thermally conductive casing to form a thermal path that transfers heat away from the logic die to the thermally conductive casing, a substrate coupled to a second face of the logic die, and a die embedded at least partially in a cavity of the substrate.