Semiconductor Die Cutting With Isolation Trenches
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Solution Overview
Problem
Conventional die cutting methods in semiconductor manufacturing face issues such as mechanical stress-induced de-lamination and cracking due to the release of interlayer stress, particularly affecting low K dielectric material layers, which reduces production yield and increases costs.
Innovation Solution
A die cutting method involving the formation of isolation trenches at the junctions of isolation and test regions, allowing for stress-free cutting by disconnecting the passivation, interconnect, and device layers, thereby preventing mechanical stress transfer during the cutting process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional blade cutting is used to mechanically cut the semiconductor wafer, then the cutting process is simple and direct, but large mechanical stress is applied to the wafer causing de-lamination and cracking between material layers
Solution Approach 1:
The patent applies preliminary action by performing laser cutting before blade cutting. The laser pre-cuts the wafer to disconnect material layers between individual chips, creating initial separation paths. This preliminary action reduces the mechanical stress required during the subsequent blade cutting process, preventing de-lamination and cracking while maintaining manufacturing simplicity.
Solution Approach 2:
The patent introduces laser cutting as an intermediary process between the wafer and the blade cutting operation. The laser acts as a mediator that pre-separates the material layers, allowing the blade to follow the predetermined path with minimal stress. This intermediary action protects the fragile low K dielectric material layers from direct mechanical stress.
2Reliability
If laser cutting is used to pre-cut the wafer before blade cutting, then de-lamination and cracking are reduced to certain degree, but the high cost of laser cutting increases chip manufacturing cost
Solution Approach 1:
The patent replaces the expensive laser cutting process with a cheaper alternative. The blade cutting tool is a more economical, disposable-like solution that achieves the same separation function without the high cost associated with laser equipment and operation. This substitution maintains production yield while significantly reducing manufacturing cost.
3Productivity
If blade cutting is performed directly on the wafer, then the cutting process is fast, but the cutting stress breaks the low K dielectric material layers
Solution Approach 1:
The patent applies preliminary action by using laser cutting to create initial separation paths before the blade cutting process. This pre-separation ensures that when the blade cuts through the wafer at high speed, the material layers are already disconnected and cannot be broken by the cutting stress. This maintains both the high cutting rate and the integrity of the low K dielectric material layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances production yield by preventing de-lamination and cracking, maintaining the integrity of low K dielectric material layers and reducing manufacturing costs through improved cutting efficiency.
Implementation Method 1
The passivation layer is etched to form trenches to expose the soldering pads located above the core regions and the test region. The passivation layer, the interconnect layer, and the device layer are etched to expose a surface of the semiconductor substrate to form isolation trenches
Data Source
AI summary
The present disclosure provides die cutting methods and semiconductor dies. A semiconductor substrate has a test region, isolation regions, and core regions. A device layer, an interconnection layer, and a soldering pad layer are formed on the semiconductor substrate. The soldering layer includes a plurality of soldering pads. A passivation layer covers the soldering pads and the interconnect layer, and is etched to form trenches on the soldering pads above the core regions and the test region. The passivation layer, the interconnect layer, and the device layer are etched to form isolation trenches at junctions of the isolation region and the test region, disconnecting the passivation layer, the interconnect layer and the device layer. A cutting process is performed along the test region, each of the semiconductor substrate, the device layer, the interconnect layer and the soldering pad layer is cut in two.