Semiconductor Die Edge Protection During Singulation
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Solution Overview
Problem
Semiconductor die edges are prone to chipping, cracking, and metal burring during the singulation process, leading to electrical shorting and weak adhesion issues due to uneven topology and the impact of saw blades or laser cutting tools.
Innovation Solution
A method involving the formation of a temporary protective planarization layer over the semiconductor die to create a planar surface, which includes depositing an encapsulant, forming a cavity, and constructing an interconnect structure with an insulating layer extending into the cavity, thereby protecting the die edge and enhancing adhesion during the build-up interconnect process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a saw blade or laser cutting tool is used to singulate the semiconductor wafer, then the wafer can be divided into individual die, but the die edges are prone to chipping, cracking, and metal burring due to the impact during the singulation process
Solution Approach 1:
A protective layer is formed over the semiconductor wafer before the singulation process. This preliminary protective action prevents chipping and cracking of die edges during the subsequent cutting operation, allowing efficient singulation while maintaining die integrity.
Solution Approach 2:
The protective layer acts as an intermediary between the saw blade/laser cutting tool and the semiconductor die. It absorbs the impact and mechanical stress during singulation, preventing direct damage to the die edges while allowing the cutting process to proceed efficiently.
2Adaptability or versatility
If the semiconductor die has an uneven or high topology, then the die can accommodate complex circuit structures, but the adhesion between the die and carrier becomes weak leading to defects during the interconnect build-up process
Solution Approach 1:
The protective layer provides uniform protection and creates a consistent surface for carrier bonding, while the underlying die can maintain its complex, non-uniform circuit topology. This local differentiation allows the die to have high circuit complexity while the bonding interface maintains uniform adhesion properties.
Solution Approach 2:
The protective layer serves as an intermediary surface between the complex-topology die and the carrier. It provides a uniform bonding interface that ensures strong adhesion, while allowing the die underneath to maintain its complex circuit structures without directly contacting the carrier.
3Productivity
If metal burring occurs along the saw street during singulation, then the cutting process can proceed, but electrical shorting occurs when forming the build-up interconnect structure
Solution Approach 1:
The protective layer converts the potentially harmful metal burring generated during singulation into a beneficial or neutral element. By preventing direct contact between the cutting tool and die, it reduces burr formation, and any burrs that do form are contained and prevented from causing electrical shorting in the interconnect structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively prevents die edge damage, reduces metal burring, and improves adhesion between the die and carrier, ensuring reliable interconnect formation and reducing defects in the semiconductor device packaging process.
Implementation Method 1
forming a protective layer over the semiconductor die
Implementation Method 2
depositing an encapsulant over the semiconductor die
Data Source
AI summary
A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant.