Semiconductor Die Configurable ESD Protection via Post-Probe Plated Pads

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Solution Overview

Problem

Semiconductor dies with ESD protection circuits connected to the same bond pad as active circuits face challenges in optimizing capacitance when packaged in different densities, leading to excess capacitance and degraded device performance.

Innovation Solution

The semiconductor device design includes separate contact pads for active and passive circuits, allowing for configurable capacitance by connecting ESD protection circuits to driver circuits only as needed, using plated pads that can be formed after probing to determine packaging density, enabling efficient wafer-level operations with identical die designs for various package configurations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ESD protection circuits are connected to the same bond pad as active circuits, then ESD protection is provided, but excess capacitance degrades device performance

Engineering Contradiction:
ImproveESD protectionVSAvoidexcess capacitance
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The bond pad is segmented into multiple separate contact pads (first contact pad for active circuit, second contact pad for ESD protection circuit). This segmentation allows independent connection of ESD protection circuits, enabling capacitance optimization by connecting ESD circuits only when needed for the given package density, thus providing protection without excess capacitance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The connection between ESD protection circuits and active circuits is made dynamic rather than fixed. By using separate contact pads and configuring connections after probing based on actual package density, the system adapts the ESD protection configuration to match the actual packaging scenario, providing optimal capacitance for each specific application.

Inventive Principle:
Principle #15Dynamics

2Reliability

If different semiconductor dies are designed for different package densities, then optimal ESD protection is achieved, but manufacturing cost increases prohibitively

Engineering Contradiction:
ImproveESD protection optimizationVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

A single universal die design with separate contact pads serves multiple package density configurations. The same die can be configured for different package densities (1, 2, 4, or more dies per package) by selectively connecting ESD protection circuits after probing, eliminating the need to design and fabricate multiple different die variants for different densities.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The connection configuration parameter is changed after probing based on the determined package density. Instead of fixing the ESD protection configuration during die design, the system allows post-probe configuration where the connection between contact pads is adjusted according to the actual package density, optimizing ESD protection for each specific application without requiring different die designs.

Inventive Principle:
Principle #35Parameter changes

3Loss of energy

If separate contact pads are used for active and passive circuits, then capacitance can be optimized, but device complexity increases

Engineering Contradiction:
Improvecapacitance optimizationVSAvoidcontact pad configuration
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

Separate contact pads are prepared in advance during die fabrication, but the actual connection configuration is deferred until after probing. This preliminary preparation of separate contact pads enables future optimization without immediately increasing complexity, as the selective connection process is automated and performed only once based on the determined package density.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10811372B2Semiconductor devices with post-probe configurability
Publication Date: 2020.10.20 MICRON TECHNOLOGY INC
  • US10811372B2 patent drawing
  • US10811372B2 patent drawing
  • US10811372B2 patent drawing

AI summary

A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements, and a plated pad electrically coupling at least a part of the first contact pad to at least a part of the second contact pad. The substrate includes a substrate contact electrically coupled to the plated pad on the die.