Semiconductor Die Packing with Hexagonal Interconnect Layout
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Solution Overview
Problem
Conventional methods for packing semiconductor devices face limitations in miniaturization due to the size of interconnects and the packaging of integrated circuits, leading to increased package size and reduced die density, which hinders the miniaturization of electronic devices.
Innovation Solution
The use of staggered hexagonal packing for interconnects and serpentine kerf cuts during dicing allows for a higher interconnect density and efficient use of die real estate, enabling more interconnects per unit area and optimizing the number of dies per wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional square grid packing is used for interconnects, then the packaging process is simple, but the interconnect density is low and package size increases
Solution Approach 1:
The patent applies asymmetric staggered hexagonal packing arrangement for interconnects, where interconnects in alternating rows are offset horizontally by half the pitch distance. This asymmetric configuration increases interconnect density by approximately 15% compared to conventional square grid packing, while maintaining manufacturability through standardized processes.
Solution Approach 2:
The patent transitions from one-dimensional linear arrangement to two-dimensional staggered hexagonal packing, utilizing both horizontal and vertical spacing optimization. By offsetting alternating rows horizontally, the design effectively uses both dimensions to maximize interconnect density within the available die area.
2Productivity
If standard linear kerf cuts are used during dicing, then the dicing process is simple, but die real estate is wasted and fewer dies per wafer are produced
Solution Approach 1:
The patent employs serpentine (curved) kerf cuts instead of straight linear cuts during the dicing process. The serpentine pattern follows a wave-like trajectory that optimizes the use of wafer real estate, allowing tighter packing of dies and increasing the number of dies per wafer by reducing wasted space between adjacent dies.
Solution Approach 2:
The serpentine kerf cut pattern is pre-planned and executed as a single continuous cutting path that anticipates the optimal positioning of multiple dies. This preliminary design of the cutting trajectory maximizes die density before the actual dicing process begins, eliminating the need for multiple separate cut operations.
Data Source
AI summary
Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.