Semiconductor Die Handling for Cleanroom-Free Hybrid Bonding

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Solution Overview

Problem

The high cost of ISO class 1 cleanroom facilities and time-consuming alignment processes hinder the widespread adoption of hybrid bonding in semiconductor manufacturing, requiring precise surface flatness and alignment accuracy for copper bumps.

Innovation Solution

A method involving the use of a temporary carrier and holder to maintain the active surface of semiconductor dies facing downward, allowing for high-density fine-pitch connections and alignment without the need for an ISO class 1 cleanroom, combined with image capture and alignment techniques to ensure precise bonding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If hybrid bonding is performed with extremely flat dielectric surface (Ra < 0.5 nm) to establish Van-der-Waal force, then bonding reliability is improved, but manufacturing cost increases due to requirement of ISO class 1 cleanroom facility

Engineering Contradiction:
Improvebonding reliabilityVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The dielectric surface is prepared and maintained in a protected state (with active surface facing downward on temporary carrier) before bonding, preventing contamination in advance. This allows achieving extremely flat surface condition without requiring ISO class 1 cleanroom during the entire manufacturing process, thus reducing manufacturing cost while maintaining bonding reliability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention applies different orientations to different surfaces: the active surface (requiring extreme flatness) faces downward on the temporary carrier during handling, while the backside surface faces upward during storage and transport. This local quality control ensures the critical bonding surface maintains its flatness without requiring expensive cleanroom facilities for the entire process

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If alignment accuracy is increased to meet small pitch copper bumps (tolerance as small as 0.3 μm), then bonding precision is improved, but production throughput decreases due to time-consuming alignment process

Engineering Contradiction:
Improvealignment accuracyVSAvoidproduction throughput
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The invention replaces time-consuming mechanical alignment processes with image capture and automated alignment techniques. By capturing images of the die and substrate and processing them computationally, the system achieves high alignment accuracy (0.3 μm tolerance) much faster than conventional mechanical methods, thus maintaining production throughput

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The invention creates optical copies (images) of the die and substrate features, then performs alignment operations on these digital representations rather than physically manipulating the actual components. This allows rapid computational alignment to achieve the required 0.3 μm tolerance without time-consuming mechanical adjustments, preserving high production throughput

Inventive Principle:
Principle #26Copying

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables high-throughput production of semiconductor packages with precise alignment and flat surface conditions, achieving production rates exceeding 1000 units per hour while maintaining surface roughness below 0.5 nm without the need for expensive cleanroom facilities.

Implementation Method 1

The temporary holder only contacts a periphery portion of the active surface of the one of the plurality of dies

Methodology Applied
Scientific EffectGravity: Gravitation

Implementation Method 2

The extremely flat surface (e.g., surface roughness Ra smaller than 0.5 nm) of the dielectric is required so that the Van-der-Waal force can be established

Methodology Applied
Scientific EffectVan-der-Waal force: Van der Waals Force

Implementation Method 3

a higher temperature annealing operation is performed to cause interdiffusion between copper-copper interface

Methodology Applied
Scientific EffectInterdiffusion: Diffusion

Data Source

PatentUS12550654B2Method for manufacturing semiconductor package
Publication Date: 2026.02.10 ADVANCED SEMICON ENG INC
  • US12550654B2 patent drawing
  • US12550654B2 patent drawing
  • US12550654B2 patent drawing

AI summary

The present disclosure provides a method for manufacturing a semiconductor package. The method includes disposing a first semiconductor substrate on a temporary carrier and dicing the first semiconductor substrate to form a plurality of dies. Each of the plurality of dies has an active surface and a backside surface opposite to the active surface. The backside surface is in contact with the temporary carrier and the active surface faces downward. The method also includes transferring one of the plurality of dies from the temporary carrier to a temporary holder. The temporary holder only contacts a periphery portion of the active surface of the one of the plurality of dies.