Semiconductor Package Die-to-Interposer Wafer Bonding

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Solution Overview

Problem

Conventional semiconductor packaging methods face limitations in providing effective thermal management and electrical connectivity while integrating passive devices, and they often require complex and costly processes for bonding semiconductor dies to packaging substrates.

Innovation Solution

The method involves bonding semiconductor dies to an interposer wafer or packaging substrate using a die-to-interposer-wafer or die-to-packaging-substrate-first bond approach, utilizing underfill materials and thermal compression or mass reflow processes, and applying mold materials to encapsulate the dies, which allows for efficient thermal management and electrical connectivity through the use of micro-bumps and through-silicon-vias.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If conventional semiconductor packaging methods are used, then manufacturing simplicity is maintained, but thermal management effectiveness and electrical connectivity are insufficient

Engineering Contradiction:

Improvethermal management effectivenessVSAvoidpackaging process complexity

Core Design Contradiction:

TemperatureVSDevice complexity

Solution Approach 1:

The packaging process is segmented into distinct stages: first bonding semiconductor dies to an interposer wafer, then bonding the interposer wafer to the packaging substrate. This segmentation allows optimized thermal and electrical pathways at each stage while maintaining overall process manageability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

An interposer wafer is introduced as an intermediary component between the semiconductor dies and the packaging substrate. This interposer provides enhanced thermal conduction pathways and improved electrical connectivity, resolving the contradiction between performance and process complexity.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If complex bonding processes are used to achieve effective thermal and electrical integration, then thermal management and connectivity improve, but manufacturing cost and process complexity increase

Engineering Contradiction:

Improvebonding yieldVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

Semiconductor dies are preliminarily bonded to the interposer wafer before final assembly with the packaging substrate. This preliminary bonding action improves alignment precision and bonding yield while enabling standardized, cost-effective manufacturing processes.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The bonding process utilizes controlled parameter changes including temperature, pressure, and reflow conditions to optimize bonding yield. These parameter optimizations improve reliability while maintaining manufacturing efficiency and cost-effectiveness.

Inventive Principle:

Principle #35Parameter changes

3Productivity

If multiple separate processes are used for bonding multiple dies, then bonding precision is maintained, but manufacturing time and complexity increase

Engineering Contradiction:

Improvepackaging process efficiencyVSAvoidbonding precision

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

Multiple die bonding operations are merged into a single integrated process where multiple semiconductor dies are simultaneously bonded to the interposer wafer. This merging approach improves manufacturing efficiency while maintaining precision through standardized bonding parameters and fixtures.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the thermal conductivity and electrical connectivity of semiconductor packages, improves bonding yields, and simplifies the packaging process by using a single underfill process for multiple dies, while integrating passive devices effectively.

Implementation Method 1

applying an underfill material between the plurality of semiconductor die and the interposer wafer

Methodology Applied

Scientific EffectCapillary action: Capillary Action

Implementation Method 2

bonding the plurality of semiconductor die to the interposer wafer, and applying an underfill material between the plurality of semiconductor die and the interposer wafer

Methodology Applied

Scientific EffectThermal compression:

Implementation Method 3

bonding the plurality of semiconductor die to the interposer wafer utilizing a mass reflow process

Methodology Applied

Scientific EffectReflow:

Implementation Method 4

A mold material may be applied to encapsulate the plurality of semiconductor die

Methodology Applied

Scientific EffectEncapsulation:

Data Source

PatentUS10283400B1Semiconductor device package and manufacturing method thereof

Publication Date: 2019.05.07 AMKOR TECH SINGAPORE HLDG PTE LTD

AI summary

Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the die and the interposer wafer. Methods and systems for a semiconductor device package with a die-to-packing substrate first bond are disclosed and may include bonding a first semiconductor die to a packaging substrate, applying an underfill material between the first semiconductor die and the packaging substrate, and bonding one or more additional die to the first semiconductor die. Methods and systems for a semiconductor device package with a die-to-die first bond are disclosed and may include bonding one or more semiconductor die comprising electronic devices to an interposer die.