Semiconductor Die Coating for Ambient Light Shielding in CSPs
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Solution Overview
Problem
Chip-scale packages (CSPs) lack adequate protection for their active surfaces due to the absence of a mold compound, leading to issues with ambient light interference and increased manufacturing complexity and cost from existing coating techniques.
Innovation Solution
A non-conductive coat is applied to the backside and sidewalls of singulated semiconductor dies using spray or immersion techniques, providing light-blocking properties without the inefficiencies of traditional reconstitution methods and allowing for laser dicing, while also considering the thickness and coverage patterns for optimal protection and cost-effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a mold compound is used to protect semiconductor dies, then protection from heat, physical trauma, and moisture is improved, but package size increases and manufacturing complexity increases
Solution Approach 1:
The patent extracts only the essential protective function from the traditional mold compound approach by applying a thin non-conductive coat (3-10 microns) directly to the backside and sidewalls of the semiconductor die, eliminating the need for thick mold compound encapsulation while maintaining protection from environmental factors
Solution Approach 2:
The patent employs a thin non-conductive film coating (3-10 microns thick) applied directly to the die surfaces, providing protective functionality without the bulk and complexity of traditional mold compound encapsulation, thereby reducing package size and simplifying structure
2Object-affected harmful factors
If traditional reconstitution methods are used to apply protective coating, then light-blocking protection is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent applies the non-conductive coat directly to the semiconductor die before final assembly, ensuring light-blocking protection is already in place before the die is mounted, eliminating the need for complex post-assembly protective structures
Solution Approach 2:
The patent changes the thickness parameter of the protective coating to a thin layer (3-10 microns) compared to traditional thick mold compound, and applies it directly to the die surface rather than using reconstitution methods, thereby reducing manufacturing complexity while maintaining light-blocking functionality
3Volume of moving object
If the inactive surface of the die is left exposed in CSP packages, then package size is reduced, but protection from ambient light is insufficient
Solution Approach 1:
The patent applies the non-conductive protective coat specifically to the backside and sidewalls of the semiconductor die where light exposure occurs, leaving the active surface exposed for electrical connections, thereby providing localized protection without increasing overall package size
Solution Approach 2:
The patent uses a thin non-conductive film (3-10 microns) applied to the backside and sidewalls of the die to block ambient light while maintaining the compact CSP form factor, achieving protection without sacrificing package miniaturization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively shields semiconductor dies from ambient light, reduces manufacturing complexity and costs, and maintains the benefits of laser dicing, such as precision and efficiency, by applying a thin, light-blocking non-conductive coat post-singulation, enhancing the performance and reliability of CSPs.
Implementation Method 1
The non-conductive coat has a thickness of less than 45 microns... effectively shields semiconductor dies from ambient light
Implementation Method 2
covering at least a portion of each of five surfaces of the semiconductor die with a non-conductive coat using a spray technique or an immersion technique
Implementation Method 3
covering at least a portion of each of five surfaces of the semiconductor die with a non-conductive coat using a spray technique or an immersion technique
Data Source
AI summary
In examples, a chip scale package (CSP) comprises a semiconductor die; a conductive terminal coupled to the semiconductor die; and a non-conductive coat covering a backside of the semiconductor die and a sidewall of the semiconductor die. The non-conductive coat has a thickness of less than 45 microns.