Semiconductor Die Layout for Longitudinal MGD Integration
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Solution Overview
Problem
The integration of a MOS gated diode (MGD) alongside a vertical transistor device in a semiconductor die poses challenges in lithography and manufacturing due to the decreasing distance between gate trenches as cell pitch decreases, particularly when arranged in a transverse direction, increasing the complexity and effort in manufacturing.
Innovation Solution
The MGD is integrated consecutive to the transistor device in the longitudinal direction of the gate trench, allowing for a common straight line alignment and shared trench structure, which simplifies lithography requirements and manufacturing processes by reducing the need for complex alignment and shared processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the MGD is arranged aside the transistor device in the transverse direction (perpendicular to gate trench extension), then the integration density is improved, but the lithography complexity and manufacturing effort increase due to decreasing distance between gate trenches
Solution Approach 1:
The patent transitions from transverse arrangement (perpendicular to gate trench extension) to longitudinal arrangement (parallel to gate trench extension). This dimensional reorientation allows the MGD to be positioned along the length of the gate trench rather than across its width, maintaining integration density while increasing the distance between adjacent gate trenches and reducing lithography complexity
Solution Approach 2:
The patent inverts the conventional arrangement by placing the MGD in the longitudinal direction opposite to the typical transverse placement. This inversion resolves the lithography challenge by ensuring that the MGD gate trench does not interfere with adjacent transistor gate trenches, as the longitudinal spacing is inherently larger than transverse spacing in standard cell designs
2Quantity of substance
If the cell pitch is decreased to increase integration density, then the quantity of devices per area is improved, but the distance between gate trenches decreases leading to increased manufacturing complexity
Solution Approach 1:
By arranging the MGD in the longitudinal direction rather than transverse direction, the patent utilizes the longer dimension of the cell structure. This allows cell pitch reduction in the transverse direction (increasing device density) without proportionally reducing the longitudinal spacing between MGD and transistor gate trenches, thereby maintaining manufacturability
Solution Approach 2:
The patent applies different spatial relationships to different device types: transverse arrangement for parallel transistor cells (maximizing density) and longitudinal arrangement for MGD integration (maintaining spacing). This localized quality differentiation allows high overall density while preserving manufacturing precision for critical gate trench spacing
Data Source
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AI summary
The disclosure relates to a semiconductor die (1) comprising a vertical transistor device (10) having a gate electrode (11) in a gate trench (12), and a MOS gated diode MGD (20) having an MGD gate electrode (21) in an MGD trench (22), wherein the gate trench (12) of the transistor device (10) has an elongated extension in a first lateral direction (31), and wherein the transistor device (10) and the MOS gated diode (20) are arranged consecutive in the first lateral direction (31).