Semiconductor Die Package Leadframe Segmentation

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Solution Overview

Problem

Existing semiconductor die packages for power MOSFETs are not optimized for size reduction and efficient heat dissipation, and their lead configurations can be difficult for OEMs to use, often requiring complex circuit board designs due to alternating gate and source leads.

Innovation Solution

A semiconductor die package design featuring a leadframe structure with separate die attach pads and leads, where the first and second control leads are positioned at opposite sides of the package, allowing for improved heat dissipation and simplified circuit board design with segregated drain and source leads, enabling more efficient current delivery and easier integration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If alternating gate and source leads are used on one side of the package, then the package can be made compact, but the circuit board design becomes more complex requiring more separated conductive pads

Engineering Contradiction:
Improvepackage sizeVSAvoidcircuit board design complexity
Core Design Contradiction:
Volume of moving objectVSDevice complexity

Solution Approach 1:

The patent segments the leads into two distinct groups: gate leads positioned at opposite corners on one side of the package, and source leads positioned at opposite corners on the other side. This spatial segmentation allows compact packaging while simplifying circuit board design, as each lead type is clustered together rather than alternating, reducing the number of separated conductive pads needed on the circuit board.

Inventive Principle:
Principle #1Segmentation

2Power

If more source leads are added to provide greater source current, then the current capacity increases, but the package size and complexity increase

Engineering Contradiction:
Improvesource current capacityVSAvoidpackage size
Core Design Contradiction:
PowerVSVolume of moving object

Solution Approach 1:

The patent merges multiple source leads into a single side of the package, allowing them to be closely spaced and efficiently routed. This merging approach enables greater source current capacity through multiple parallel leads while maintaining a compact package size, as the source leads are consolidated rather than distributed throughout the package structure.

Inventive Principle:
Principle #5Merging (Combining)

3Volume of moving object

If the package is made smaller and thinner, then it can be used in compact devices, but heat dissipation becomes more difficult

Engineering Contradiction:
Improvepackage sizeVSAvoidheat dissipation efficiency
Core Design Contradiction:
Volume of moving objectVSTemperature

Solution Approach 1:

The patent positions gate leads and source leads at opposite corners on opposite sides of the package, utilizing the three-dimensional space efficiently. This dimensional arrangement allows the leads to extend outward from the compact package body, providing thermal pathways in multiple directions and improving heat dissipation from the small, thin package structure through enhanced surface area exposure and thermal conduction paths.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8754509B2Package with multiple dies
Publication Date: 2014.06.17 SEMICON COMPONENTS IND LLC
  • US8754509B2 patent drawing
  • US8754509B2 patent drawing
  • US8754509B2 patent drawing

AI summary

A semiconductor die package is disclosed. It includes a leadframe structure comprising a first die attach pad and a second die attach pad. A plurality of leads extend from the first and second die attach pads. The plurality of leads includes at least a first control lead and a second control lead. A first semiconductor die including a first device is mounted on the first die attach pad, and a second semiconductor die has a second device is mounted on the second die attach pad. A housing is provided in the semiconductor die package and protects the first and second dies. The housing may have an exterior surface and at least partially covers the first semiconductor die and the second semiconductor die. The first control lead and the second control lead are at opposite sides of the semiconductor die package.