Semiconductor Die Package Conductive Node Clip Parasitic Inductance
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Solution Overview
Problem
Conventional semiconductor die packages for synchronous buck converters suffer from high parasitic inductance, reduced high-frequency power efficiency, thermal performance, and package reliability due to bond wires and multi-die paddle configurations, which are not well-suited for moderate to high current carrying and lead to larger package sizes and sensitivity to environmental factors.
Innovation Solution
A semiconductor die package design featuring a substrate with a conductive node clip that electrically communicates between the output region of a low-side MOSFET and the input region of a high-side MOSFET, reducing parasitic inductance and incorporating a leadframe structure with molding to enhance heat dissipation and package reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bond wires are used to connect MOSFETs in conventional packages, then the package can be assembled, but parasitic inductance increases and high-frequency power efficiency decreases
Solution Approach 1:
The patent extracts and eliminates bond wires from the conventional package structure. Instead of using bond wires to connect MOSFETs, the invention uses a substrate with direct electrical connections, removing the source of parasitic inductance and energy loss while maintaining package assembly capability
Solution Approach 2:
The patent introduces a substrate as an intermediary component that provides direct electrical connections between MOSFETs. This substrate acts as a mediator that eliminates the need for bond wires, reducing parasitic inductance while enabling proper signal and power transmission between devices
2Reliability
If individual die paddles are used to support MOSFETs, then each die can be mounted, but the package size increases and manufacturing complexity increases
Solution Approach 1:
The patent merges multiple individual die paddle structures into a single integrated substrate. This consolidation provides support for all MOSFETs while reducing the overall package footprint and simplifying the structural complexity compared to using separate paddles for each die
3Ease of manufacture
If conventional multi-die paddle packages are used, then devices can be mounted, but parasitic inductance increases and thermal performance deteriorates
Solution Approach 1:
The patent extracts and removes the multi-die paddle structure that causes thermal performance issues. By eliminating this conventional mounting approach, the invention reduces thermal resistance and improves heat dissipation while maintaining device mounting capability through the substrate structure
Solution Approach 2:
The patent transitions from a lateral arrangement of dies on separate paddles to a vertical stacking configuration on a single substrate. This dimensional change improves thermal pathways by enabling better heat flow from the devices to the substrate and ultimately to the heat sink
Data Source
AI summary
A semiconductor die package capable of being mounted to a motherboard is disclosed. The semiconductor die package includes a substrate, and a first semiconductor die mounted on the substrate, where the first semiconductor die includes a first vertical device comprising a first input region and a first output region at opposite surfaces of the first semiconductor die. The semiconductor die package includes a second semiconductor die mounted on the substrate, where second semiconductor die comprises a second vertical device comprising a second input region and a second output region at opposite surfaces of the second semiconductor die. A substantially planar conductive node clip electrically communicates the first output region in the first semiconductor die and the second input region in the second semiconductor die. The first semiconductor die and the second semiconductor die are between the substrate and the conductive node clip.