Semiconductor Die Rear Surface Segmentation for Solder Contamination Control
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Solution Overview
Problem
Existing semiconductor device assembly manufacturing processes face challenges in ensuring reliable connections and preventing contamination during soldering, particularly due to sawing defects and impurity diffusion from the solder material into the semiconductor die, which can damage the conductive structure and affect the integrity of the semiconductor device.
Innovation Solution
A semiconductor device assembly design featuring a lattice-like separation trench on the rear side of the semiconductor wafer, with a conductive structure extending into the trench and a kerf portion forming a grid to mechanically connect the dies, ensuring that the solder material does not contact the outer surface prone to sawing defects, and using a conductive structure with sub-layers to prevent impurity diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the semiconductor die is soldered directly to the chip carrier with the conductive structure exposed, then electrical connection is achieved, but solder material contacts the outer surface prone to sawing defects causing contamination and mechanical strain
Solution Approach 1:
The patent segments the rear surface into different elevation levels: a central surface portion at a first elevation and an outermost surface portion at a second elevation. This segmentation allows the conductive structure to be positioned only on the central surface portion, preventing solder material from contacting the outermost surface portion that is prone to sawing defects, thus resolving the contradiction between achieving electrical connection and preventing contamination
Solution Approach 2:
The patent introduces an intermediate surface portion with a tilted profile that connects the central and outermost surface portions. This intermediate structure acts as a mediator that guides the transition between levels while ensuring the conductive structure remains protected on the central portion, allowing solder to flow onto the chip carrier without contacting the contaminated outermost surface
2Reliability
If the conductive structure covers the entire rear surface including outer edges, then electrical connection is maximized, but the outer surface prone to sawing defects is exposed to solder material causing impurity diffusion
Solution Approach 1:
The patent applies local quality by positioning the conductive structure only on the central surface portion where it is needed for electrical connection, while leaving the outermost surface portion without conductive structure. This localized placement ensures that solder material cannot diffuse impurities into the conductive structure through defects on the outer surface, resolving the contradiction between maximizing electrical connection and preventing impurity diffusion
3Ease of manufacture
If the outer surface is left exposed for mechanical connection, then assembly is simplified, but sawing defects on the outer surface are exposed to solder material causing contamination
Solution Approach 1:
The patent resolves the contradiction by adding a vertical dimension to the surface structure, creating a stepped profile where the central surface portion is at a higher elevation than the outermost surface portion. This dimensional change allows the outermost surface to remain exposed for mechanical connection purposes while the elevated central surface with conductive structure remains protected from solder contact, thus maintaining assembly simplicity while preventing contamination
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively prevents solder-induced contamination and mechanical strain on pre-damaged semiconductor die regions, ensuring reliable electrical and mechanical connections while maintaining the integrity of the semiconductor device by spacing the outer surface from the solder material and using a conductive structure to bar impurities.
Implementation Method 1
A soldered layer mechanically and electrically connects the chip carrier and the conductive structure
Implementation Method 2
The conductive structure covers the central surface portion and at least a section of an intermediate surface portion
Data Source
AI summary
A semiconductor device includes a chip carrier and a semiconductor die with a semiconductor portion and a conductive structure. A soldered layer mechanically and electrically connects the chip carrier and the conductive structure at a soldering side of the semiconductor die. At the soldering side an outermost surface portion along an edge of the semiconductor die has a greater distance to the chip carrier than a central surface portion. The conductive structure covers the central surface portion and at least a section of an intermediate surface portion tilted to the central surface portion. Solder material is effectively prevented from coating such semiconductor surfaces that are prone to damages and solder-induced contamination is significantly reduced.