Semiconductor Die Six-Sided Encapsulation via Segmented Trenching
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Solution Overview
Problem
Existing semiconductor packaging methods, such as six-sided chip scale packages, face challenges in cutting deep trenches in wafers, leading to thin dies that are prone to warping and breakage due to thermal expansion differences between the polymeric material and the dies, especially when trenches are deeper than 250 microns.
Innovation Solution
A method involving forming first and second trenches on opposite sides of a semiconductor wafer, filling them with protective materials, and then thinning the wafer to align the trenches for complete encapsulation, providing pseudo six-sided protection without the need for extremely thin dies, using a combination of trench depths and polymeric materials with controlled thermal expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep trenches are cut into the wafer to completely encapsulate dies, then encapsulation completeness is improved, but die thickness must be reduced below 250 microns which causes warping and breakage
Solution Approach 1:
The encapsulation process is divided into two separate stages: first cutting trenches from the front side and filling with polymeric material, then after thinning the wafer, cutting additional trenches from the back side and filling with more polymeric material. This segmentation allows each trench cutting operation to be performed on a thicker wafer, avoiding the need to cut deep trenches through the entire wafer thickness which would require excessively thin final die structure.
Solution Approach 2:
The first trenches are cut and filled with polymeric material before the wafer is thinned. This preliminary encapsulation provides initial protection and structural support to the die, allowing the wafer to be thinned to the desired final thickness without compromising die integrity during subsequent handling and back-side trench processing.
2Ease of manufacture
If wafer is thinned to less than 250 microns to expose trenches for backside coating, then trench accessibility is improved, but die becomes susceptible to thermal expansion stress and warping
Solution Approach 1:
The wafer thickness parameter is optimized to be between 250-350 microns, which is thicker than conventional approaches. This parameter change provides sufficient mechanical strength to resist thermal expansion stresses while still allowing back-side trench cutting and filling operations to be performed effectively, achieving both manufacturability and thermal stability.
3Reliability
If polymeric material is used to fill trenches, then encapsulation is achieved, but thermal expansion coefficient mismatch causes warping in thin dies
Solution Approach 1:
Multiple layers of polymeric material are applied in separate stages, with each layer potentially having different properties. The composite structure of multiple polymeric layers provides encapsulation protection while distributing thermal stress more evenly than a single thick layer would, reducing warping in the final packaged die.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in robust semiconductor components with virtual complete six-sided encapsulation, reducing warpage and breakage risks, and allows for uniform loading to mitigate thermal stresses, enabling more reliable and durable packaging.
Implementation Method 1
depositing a polymeric material on the active side to fill the trenches and cover the dies
Implementation Method 2
The wafer is then thinned from the backside until the trenches are exposed
Implementation Method 3
because the polymeric material and the dies have significantly different thermal expansion coefficients, thermal cycling can cause extensive warping and even breakage of the very thin dies
Data Source
AI summary
Packaged semiconductor components and methods for manufacturing packaged semiconductor components. In one embodiment a semiconductor component comprises a die having a semiconductor substrate and an integrated circuit. The substrate has a first side, a second side, a sidewall between the first and second sides, a first indentation at the sidewall around a periphery of the first side, and a second indentation at the sidewall around a periphery of the second side. The component can further include a first exterior cover at the first side and a second exterior cover at the second side. The first exterior cover has a first extension in the first indentation, and the second exterior cover has a second extension in the second indentation. The first and second extensions are spaced apart from each other by an exposed portion of the sidewall.


