3D Semiconductor Die Stacking with Oval Pillars

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Solution Overview

Problem

As semiconductor devices continue to shrink in size, challenges arise in integrating more components into a given area while minimizing stress and defects, and existing methods face inefficiencies in die stacking and packaging processes.

Innovation Solution

The formation of die stacking structures involves creating conductive pillars on a back-side redistribution structure, attaching active device dies with conductive pillars, and forming a front-side redistribution structure to interconnect them, allowing for minimal area packaging with a single molding and grinding step, and using oval-shaped or round-shaped pillars to reduce stress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but stress and defects increase

Engineering Contradiction:
Improveintegration densityVSAvoidstress and defects
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent transitions from planar integration to three-dimensional die stacking, moving components into the vertical dimension. Multiple dies are stacked and interconnected through conductive pillars, allowing higher integration density without further reducing lateral feature sizes, thereby avoiding the stress and defect issues associated with miniaturization.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent divides the integrated circuit into multiple separate dies that are stacked and interconnected. Each die can be optimized independently, and the segmentation allows for better stress management compared to a single large-scale integrated circuit where miniaturization causes stress accumulation.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If conventional die stacking methods are used, then multiple dies can be integrated, but the process requires multiple molding and grinding steps increasing complexity

Engineering Contradiction:
Improvenumber of integrated diesVSAvoidnumber of molding and grinding steps
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent combines multiple die stacking operations into a single molding process. Multiple dies are stacked and interconnected within one mold cavity, allowing simultaneous formation of the encapsulant and interconnect structures. This eliminates the need for separate molding and grinding steps for each die layer, reducing process complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent performs preliminary preparation of dies with conductive pillars and bonding surfaces before final stacking. The dies are pre-configured with alignment features and interconnect structures, allowing them to be stacked in a single operation without requiring subsequent alignment or bonding steps, thereby simplifying the overall process.

Inventive Principle:
Principle #10Preliminary action

3Ease of manufacture

If rectangular conductive pillars are used, then manufacturing is simpler, but stress in the packaged device increases

Engineering Contradiction:
Improveconductive pillar fabricationVSAvoiddevice stress
Core Design Contradiction:
Ease of manufactureVSStress or pressure

Solution Approach 1:

The patent employs oval-shaped conductive pillars instead of rectangular ones. The oval geometry provides asymmetric stress distribution that better accommodates thermal expansion differences between stacked dies, reducing overall device stress while remaining compatible with standard manufacturing processes.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent modifies the geometric parameters of conductive pillars from rectangular to oval cross-sections. This parameter change optimizes the stress distribution characteristics of the pillars, allowing them to better accommodate thermal and mechanical stresses in the packaged device while maintaining ease of manufacture through standard patterning processes.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11139249B2Semiconductor devices and methods of forming the same
Publication Date: 2021.10.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11139249B2 patent drawing
  • US11139249B2 patent drawing
  • US11139249B2 patent drawing

AI summary

A packaged semiconductor device including a first die attached to a redistribution structure, a second die attached to the first die, and a molding compound surrounding the first die and the second die and a method of forming the same are disclosed. In an embodiment, a method includes forming first conductive pillars over and electrically coupled to a first redistribution structure; attaching a first die to the first redistribution structure, the first die including second conductive pillars; attaching a second die to the first die adjacent the second conductive pillars; encapsulating the first conductive pillars, the first die, and the second die with an encapsulant; forming a second redistribution structure over the encapsulant, the first conductive pillars, the first die, and the second die; and bonding a third die to the first redistribution structure.