Semiconductor Die Pre-Packaging Functional Test via JTAG Boot
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Solution Overview
Problem
Conventional quality control assessments for semiconductor chips are inadequate, as they cannot perform comprehensive tests on bare silicon chips before packaging, leading to potential manufacturing escapes and costly faults that manifest during customer use.
Innovation Solution
A method and system for testing semiconductor circuits involve attaching a non-packaged semiconductor circuit to a test bed, loading computer instructions via a JTAG interface, and operating the circuit in a test boot mode to perform functional tests without packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional quality control assessments (ATPG scan, memory BIST, high speed IO tests, JTAG) are used to test semiconductor chips, then basic hardware and firmware elements can be tested, but comprehensive functional testing cannot be performed on bare silicon chips before packaging, leading to manufacturing escapes
Solution Approach 1:
The patent applies preliminary action by performing comprehensive functional testing on bare silicon chips before they are packaged. The test bed enables execution of test software and firmware on the chip prior to packaging, allowing faults to be identified early in the manufacturing process. This eliminates the need to wait until after packaging to discover defects, thereby improving both reliability and productivity by preventing manufacturing escapes.
2Adaptability or versatility
If larger dies are designed to contain all circuits (monolithic SoC), then integration is achieved, but manufacturing complexity and error probability increase due to reticle size constraints
Solution Approach 1:
The patent applies segmentation by enabling functional testing of individual chiplets or modules before they are packaged into a complete system. The test bed can independently test each chiplet's functionality, allowing the system to accommodate disaggregated architectures where complex functionality is divided across multiple smaller, more manageable units. This reduces the complexity of individual dies while maintaining overall system adaptability.
3Ease of operation
If testing is performed after packaging, then chiplets can be tested in their final configuration, but faults in non-faulty chiplets cannot be detected and the entire package becomes unusable
Solution Approach 1:
The patent applies preliminary action by performing comprehensive functional testing on each chiplet before packaging. The test bed enables execution of test software that can detect faults in individual chiplets prior to assembly. This ensures that only fault-free chiplets are packaged, maintaining the usability and reliability of the final package. If a chiplet has faults, they are identified during preliminary testing rather than after packaging, preventing waste of the entire package.
Data Source
AI summary
A system and method are provided that enables a processor to undergo a functional test of its circuits prior to attachment to a semiconductor package and prior to use in a computing platform. The method of testing chips includes attaching a non-packaged semiconductor circuit to a test bed, loading computer instructions into a memory of the non-packaged semiconductor circuit, and operating the non-packaged semiconductor circuit in a test boot mode and executing the computer instructions in that mode. The operation logs one or more events of the execution of the instructions in the test boot mode and transmits the logs of the one or more events from the non-packaged semiconductor circuit via a joint test action group (JTAG) interface or a universal asynchronous receiver/transmitter (UART) interface.