Semiconductor Layer Stack Dielectric Filling for Flat CFET Profiles
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Solution Overview
Problem
Existing semiconductor manufacturing processes for complementary FETs (CFETs) are complex and result in suboptimal electrical performance due to challenges in forming high-quality dielectric layers and maintaining structural integrity during etching and deposition steps.
Innovation Solution
A method involving a layer stack with alternating sacrificial layers protected by liner layers, using Ultra Chemical Vapor Deposition (UCVD) to deposit dielectric material in cavities and recesses, ensuring flat profiles and reducing erosion, thereby simplifying processing and enhancing electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional deposition methods are used to form dielectric layers, then the manufacturing process is simpler, but the dielectric layers exhibit erosion and non-flat profiles resulting in suboptimal electrical performance
Solution Approach 1:
The patent segments the deposition process into two distinct stages: first depositing dielectric material to fill cavities and form initial layers, then performing a second deposition to create flat-profile cap layers. This segmentation allows each deposition to be optimized for its specific purpose, resolving the contradiction between achieving high dielectric quality and maintaining process simplicity.
Solution Approach 2:
The patent performs preliminary actions by first forming cavities through selective removal of sacrificial layers, then depositing dielectric material to fill these cavities before subsequent planarization steps. This preliminary cavity formation and filling approach enables better control over dielectric layer quality and flatness, addressing the erosion and profile issues while managing process complexity.
2Stability of the object's composition
If multiple sacrificial layers are used to form complex structures, then the structural integrity is improved, but the etching process becomes more complex and time-consuming
Solution Approach 1:
The patent introduces liner layers as intermediary protective barriers between sacrificial layers and etchants. These liner layers enable selective etching of specific sacrificial materials without affecting adjacent structures, thereby maintaining structural integrity during the etching process while managing the complexity and time required for multi-layer processing.
Solution Approach 2:
The patent applies local quality by using different sacrificial materials (first and second sacrificial semiconductor materials) with distinct etch selectivities in different regions of the structure. This allows targeted removal of specific layers while preserving others, maintaining overall structural integrity while enabling efficient selective etching processes.
3Manufacturing precision
If conventional CVD methods are used for dielectric deposition, then the process is faster, but the deposited layers exhibit erosion and poor flatness
Solution Approach 1:
The patent employs periodic action by conducting deposition in multiple sequential steps rather than a single continuous process. The first deposition step fills cavities and forms base dielectric layers, followed by a second deposition step that specifically targets flatness for subsequent processing. This periodic, multi-stage approach achieves superior flatness while managing overall deposition time.
Solution Approach 2:
The patent applies parameter changes by modifying deposition conditions between different deposition steps. By adjusting deposition parameters (such as gas flow rates, temperature, or pressure) for different stages, the process optimizes both the filling of cavities and the formation of flat cap layers, achieving high precision without excessive time penalty.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method reduces processing steps, minimizes layer erosion, and achieves improved electrical performance by forming high-quality dielectric layers with flat profiles, facilitating efficient fabrication of CFETs and other horizontal channel FET devices.
Implementation Method 1
depositing dielectric material in the at least one cavity and depositing dielectric material in the recesses of the first sacrificial layers is performed by a first chemical vapor deposition (CVD) method. The first CVD method comprises reacting, as a film-forming gas, an oxygen-containing silicon compound gas with a non-oxidizing hydrogen-containing gas in a state in which at least the non-oxidizing hydrogen-containing gas is plasmarized, to form a film of a flowable silanol compound, and, subsequently, annealing the film of flowable silanol compound into the first dielectric material.
Implementation Method 2
reacting, as a film-forming gas, an oxygen-containing silicon compound gas with a non-oxidizing hydrogen-containing gas in a state in which at least the non-oxidizing hydrogen-containing gas is plasmarized
Implementation Method 3
annealing the film of flowable silanol compound into the first dielectric material
Data Source
AI summary
The present disclosure provides a method for forming a semiconductor structure. The method includes forming a layer stack on a substrate. The layer stack includes a first sub-stack, a second sub-stack on the first sub-stack and includes a plurality of sacrificial layers alternating between first and second sacrificial layers, and a third sub-stack on the second sub-stack. The method includes forming recesses in the first sacrificial layers, removing the at least one second sacrificial layer, depositing dielectric material in the at least one cavity, and depositing dielectric material in the recesses of the first sacrificial layers, wherein at least one of the acts of depositing dielectric material in the at least one cavity, and depositing dielectric material in the recesses of the first sacrificial layers, is performed by a first chemical vapor deposition method, CVD method.