Semiconductor Structure With Dielectric S/D Isolation for Off-State Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As transistors, such as multi-gate field effect transistors, are scaled down in dimension, off-state current leakage in the substrate becomes a significant concern, necessitating improvements to maintain device performance and efficiency.
Innovation Solution
A dielectric region is formed at the bottom of the source/drain regions in the substrate by ion implantation and subsequent oxidation, effectively blocking current leakage when the gate is in the 'off' state, thereby enhancing device performance and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimension is scaled down, then production efficiency is improved and costs are lowered, but off-state current leakage increases
Solution Approach 1:
The patent applies local quality by forming a dielectric region specifically at the bottom of the source/drain regions in the substrate. This localized modification targets the specific area where current leakage occurs (substrate region beneath source/drain) without requiring global changes to the entire transistor structure, thus maintaining scaling benefits while addressing the leakage issue locally.
Solution Approach 2:
The dielectric region acts as an intermediary layer between the source/drain regions and the substrate. This intermediary structure blocks the harmful current leakage path from source to drain through the substrate while maintaining the electrical functionality of the transistor, effectively mediating between the conflicting requirements of scaled dimensions and leakage prevention.
2Length of moving object
If transistor dimension is scaled down, then geometry size is decreased, but off-state current leakage becomes significant
Solution Approach 1:
The dielectric region is formed locally at the bottom of the source/drain regions, providing targeted leakage blocking only where needed. This local modification allows the transistor to maintain its scaled geometry for high density while adding functionality specifically at the leakage-prone substrate interface.
Solution Approach 2:
The patent addresses the 2D scaling limitation by introducing a vertical dimension solution - forming a dielectric region in the vertical direction at the bottom of source/drain. This vertical intervention blocks current leakage paths without requiring horizontal dimension changes, thus maintaining the scaled geometry while improving reliability.
3Reliability
If a dielectric region is formed by ion implantation and oxidation, then current leakage is blocked, but manufacturing process complexity increases
Solution Approach 1:
The ion implantation is performed as a preliminary action before source/drain epitaxial growth, preparing the substrate region for subsequent oxidation. This sequencing allows the dielectric region formation to be integrated into the existing manufacturing flow without requiring separate dedicated process steps, thereby limiting the increase in manufacturing complexity.
Solution Approach 2:
The patent uses parameter changes (ion implantation followed by oxidation) to transform the substrate region into a dielectric region. By changing the physical and chemical parameters of the substrate through controlled ion implantation and oxidation, the desired leakage-blocking property is achieved using established semiconductor processing techniques rather than requiring entirely new manufacturing approaches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dielectric region effectively blocks current leakage from the source to drain region when the gate is off, improving device performance and reducing power consumption, while maintaining manufacturing cost-effectiveness.
Implementation Method 1
converting the implanted regions into dielectric regions by subjecting the implanted regions to an oxidation process
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a first source/drain epitaxial feature formed over a substrate, a second source/drain epitaxial feature formed over the substrate, two or more semiconductor layers disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a gate electrode layer surrounding a portion of one of the two or more semiconductor layers, a first dielectric region disposed in the substrate and in contact with a first side of the first source/drain epitaxial feature, and a second dielectric region disposed in the substrate and in contact with a first side of the second source/drain epitaxial feature, the second dielectric region being separated from the first dielectric region by a substrate.