Semiconductor Dielectric Void Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
Current semiconductor technologies face challenges in reducing parasitic capacitance due to the limitations in adjusting the connection geometry of conductors, which affects signal transmission speed, as parasitic capacitance is directly proportional to the dielectric constant of the insulating dielectric layer.
Innovation Solution
Introducing air voids into the dielectric layer by forming a semiconductor structure with a groove and alternately blowing precursors to create dielectric layers, ensuring the region enclosed by the first sub-sidewall and the bottom of the groove has a low dielectric constant, thereby reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a low-k material is used as an insulating dielectric layer, then parasitic capacitance is reduced and signal transmission speed is improved, but the dielectric constant cannot be reduced further due to technical limitations in adjusting connection geometry
Solution Approach 1:
The patent introduces air voids into the dielectric layer to create a porous structure. By forming voids within the dielectric material, the effective dielectric constant is reduced because air has a dielectric constant close to 1, which is lower than solid dielectric materials. This porous structure allows further reduction of parasitic capacitance beyond what can be achieved by geometry adjustment alone.
Solution Approach 2:
The patent creates a composite dielectric structure combining solid dielectric material and air voids. This composite approach allows tuning of the effective dielectric constant by controlling the volume fraction and distribution of air voids, enabling customized dielectric properties that balance signal transmission speed and manufacturing feasibility.
2Object-affected harmful factors
If air voids are introduced into the dielectric layer, then the dielectric constant is reduced, but the structural stability and process control become more challenging
Solution Approach 1:
The patent applies local quality by creating air voids at specific locations within the dielectric layer rather than uniformly throughout. The void formation is controlled to occur in regions where it most effectively reduces parasitic capacitance while maintaining structural integrity in load-bearing areas. This localized approach allows optimization of electrical performance without compromising overall structural stability.
Solution Approach 2:
The patent performs preliminary action by forming the air voids during the dielectric layer deposition process itself, rather than attempting to create voids afterward. By controlling void formation during the ALD or CVD process through precursor flow rate management, the structure is created in its final configuration, ensuring both the desired dielectric properties and structural stability from the outset.
3Productivity
If precursors are blown at high flow rate, then dielectric layer formation is faster, but air voids cannot be properly formed in the required region
Solution Approach 1:
The patent employs periodic action by alternately blowing precursors at different flow rates during the dielectric layer formation process. Specifically, the first precursor is blown at a flow rate below a threshold value to enable void formation, then the second precursor is blown to complete the dielectric layer. This periodic variation in flow rate allows both void formation and complete layer deposition to be achieved systematically.
Solution Approach 2:
The patent applies partial action by using a lower-than-normal precursor flow rate specifically for the first precursor during the critical void formation stage. Rather than maintaining high flow rate throughout the entire deposition process, the flow rate is temporarily reduced to the extent necessary to allow air voids to form in the first sub-sidewall region, then恢复正常 for complete layer formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the dielectric constant of the dielectric layer, improving signal transmission speed by minimizing parasitic capacitance and ensuring structural stability and process feasibility.
Implementation Method 1
blowing a first precursor to a surface of the substrate at a flow rate less than a preset value, so that the first precursor is attached to a top surface of the substrate and the second sub-sidewall
Implementation Method 2
blowing a second precursor to the surface of the substrate, so that the second precursor reacts with the first precursor to form a dielectric layer
Data Source
AI summary
Embodiments of the present application provide a semiconductor structure and its formation method. The method includes: the substrate being provided with a groove, a sidewall of the groove including a first sub-sidewall and a second sub-sidewall that extend upwards from a bottom of the groove sub-sidewall; blowing a first precursor to a surface of the substrate, so that the first precursor is attached to a top surface of the substrate and the second sub-sidewall; blowing a second precursor to the surface of the substrate, so that the second precursor reacts with the first precursor to form a dielectric layer; alternately blowing the first precursor and the second precursor to the surface of the substrate to form a plurality of dielectric layers until a top opening of the groove is blocked, a region enclosed by the first sub-sidewall, the dielectric layer and the bottom of the groove forming a void.