Semiconductor Structure With Different-Net Via Pair Layout
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Solution Overview
Problem
The existing semiconductor integrated circuit (IC) designs face challenges in reducing the space between metal lines, leading to larger cell areas and lower metal line density due to excessive spacing, which hinders the miniaturization and complexity of ICs.
Innovation Solution
The implementation of a different-net via pair configuration, where two vias and two metal lines connected to different nets are arranged with a distance within 1.5 poly pitches, allowing the metal lines to extend in opposite directions, thereby reducing the space between them and improving metal line density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional metal line layout is used with standard spacing, then manufacturing simplicity is maintained, but metal line density is low and cell area is large
Solution Approach 1:
The patent applies dimensionality change by introducing a new spatial arrangement dimension for metal lines. Specifically, it positions metal lines at different vertical levels (first metal line at higher level, second metal line at lower level) and uses via structures to connect them, transforming a two-dimensional planar layout problem into a three-dimensional spatial arrangement. This enables higher metal line density without increasing the horizontal cell area, as lines can overlap or run parallel in adjacent layers rather than requiring horizontal separation.
2Area of stationary object
If metal lines are placed closer together to reduce cell area, then cell area decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent resolves the precision constraint by moving the spacing problem from the horizontal plane to the vertical dimension. Metal lines are separated into different layers with via structures connecting them, allowing horizontal proximity without direct interference. The manufacturing precision requirement shifts from controlling horizontal spacing to controlling vertical alignment and via placement, which can be more easily managed through standard multi-layer fabrication processes.
Solution Approach 2:
The via structure acts as an intermediary element that connects metal lines from different layers. This mediator allows the metal lines to be positioned close horizontally while maintaining electrical connection through the vertical via pathway, effectively decoupling the horizontal spacing requirement from the electrical connectivity requirement and reducing the cell area.
3Productivity
If more metal lines are packed into the same area to increase IC complexity, then functional density increases, but space between metal lines becomes insufficient
Solution Approach 1:
The patent enables increased functional density by utilizing the vertical dimension for metal line routing. Multiple metal lines can occupy the same horizontal footprint by being placed in adjacent layers, connected through via structures. This three-dimensional arrangement effectively multiplies the available routing space, allowing more interconnections within the same cell area without reducing the required spacing between lines in any given layer.
Data Source
AI summary
A semiconductor structure includes a plurality of vias and a metal layer. The vias disposed on a semiconductor substrate. The metal layer has a plurality of metal lines and at least one transmission gate line region. The metal lines are connected to the vias. The at least one transmission gate line region is connected to at least one transmission gate corresponding to at least one transmission gate circuit. The transmission gate line region includes at least one different-net via pair. The different-net via pair has two metal lines and each of the two metal lines is connected to a via respectively. The two metal lines extend along a first axis but toward opposite directions. A distance between the two vias of the different-net via pair is within about 1.5 poly pitch.