Semiconductor Devices With Differential Doping For Selective Etching
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Solution Overview
Problem
3D semiconductor devices with stacked tiers and vertical channels face structural and manufacturing challenges due to interfaces within channels, which hinder independent gate control and increase complexity in the manufacturing process.
Innovation Solution
The implementation of differential doping configurations in select gate source, control gate, and select gate drain tiers, along with etch stop structures, allows for selective etching and the formation of monolithic channels with reduced interfaces, enabling independent gate control by using etching solutions like tetramethylammonium hydroxide (TMCH).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stacked tiers with vertical channels are implemented in 3D semiconductor devices, then device capacity and integration density are improved, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The patent segments the gate structure into multiple tiers (first select gate tier, control gate tier, second select gate tier) with distinct doping configurations. Each tier can be independently controlled, allowing complex 3D functionality to be achieved through modular segmentation rather than monolithic structures, thereby reducing manufacturing complexity while maintaining high device capacity
Solution Approach 2:
Different doping configurations are applied to different tiers: the first select gate tier has a first doping configuration, the control gate tier has a second doping configuration, and the second select gate tier has a third doping configuration. This local differentiation enables independent gate control and simplifies the manufacturing process by allowing selective etching and processing of specific regions
2Ease of operation
If interfaces are reduced within channels through monolithic channel formation, then independent gate control is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes differential doping configurations as a parameter change to enable selective etching. By varying the doping type and concentration across different tiers, the etching process can be tuned to remove specific materials selectively, forming monolithic channels with reduced interfaces. This parameter-based control achieves high manufacturing precision through chemical differentiation rather than relying solely on geometric precision
3Ease of manufacture
If differential doping configurations are applied to select gate tiers, then selective etching capability is improved, but device structure complexity increases
Solution Approach 1:
The differential doping configurations are applied in advance during the formation of the gate tiers, before the etching process. This preliminary action prepares the structure for selective etching by creating inherent chemical differences between tiers, allowing subsequent etching steps to proceed with high selectivity without requiring complex real-time control during manufacturing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of 3D semiconductor devices with integrated channels that have reduced interfaces and allow for independent gate control, simplifying the manufacturing process and improving the structural integrity of the devices.
Implementation Method 1
selective etching and the formation of monolithic channels with reduced interfaces, enabling independent gate control by using etching solutions like tetramethylammonium hydroxide (TMCH)
Data Source
AI summary
Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.