Semiconductor Device Differential Wiring Impedance Control
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Solution Overview
Problem
High-speed differential signal transmission in semiconductor devices faces challenges due to impedance discontinuities between wiring pairs, leading to signal reflection and reduced return loss characteristics, especially when connecting semiconductor chips to wiring substrates.
Innovation Solution
The semiconductor device incorporates a differential pair wiring configuration with specific impedance adjustments, including detouring portions with increased clearance and meandering shapes to manage impedance values, creating additional impedance discontinuities that cancel signal reflections and improve transmission characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If parallel wiring configuration is used for differential signal transmission, then signal transmission speed is improved, but impedance discontinuity causes signal reflection and degraded return loss characteristics
Solution Approach 1:
The patent applies local quality by creating detour portions at specific locations along the parallel wirings. These detour portions locally increase the clearance between conductors only at impedance discontinuity points, rather than uniformly increasing clearance throughout the entire wiring length. This localized modification adjusts impedance at critical points while maintaining the overall parallel configuration for high-speed transmission.
Solution Approach 2:
The patent changes the geometric parameter (clearance distance) between the first and second wirings at specific locations. By increasing the clearance at detour portions, the differential impedance is adjusted to match between the parallel wiring section and the wiring substrate connection, reducing impedance discontinuity and improving return loss characteristics while maintaining high-speed transmission capability.
2Reliability
If clearance between differential pair wirings is increased, then impedance matching is improved, but wiring area increases
Solution Approach 1:
Instead of uniformly increasing clearance between wirings across the entire substrate, the patent implements detour portions that locally increase clearance only at specific positions where impedance matching is needed. This approach achieves the required impedance matching while minimizing the overall wiring area occupation.
Solution Approach 2:
The detour portions introduce curved or meandering paths for the wirings rather than straight parallel lines. This curvature allows the wirings to detour around each other, increasing the effective clearance at critical points without proportionally increasing the linear footprint of the wiring structure.
Data Source
AI summary
Signal transmission characteristics of a semiconductor device are improved. A plurality of wirings of a wiring substrate on which a semiconductor chip is mounted include a first wiring and a second wiring that constitute a differential pair for use in transmitting a differential signal. Moreover, the first wiring and the second wiring respectively have first portions that extend in parallel with each other with a first clearance and second portions that are formed on the same wiring layer as the first portions, and extend in parallel with each other with a second clearance and third portions that are installed between the first portions and the second portions and designed to detour in such directions as to allow the mutual clearance to become greater than the first clearance and the second clearance.