Semiconductor Device Diffusion Restraining Layer

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Solution Overview

Problem

Transistors face challenges in reducing short channel effects due to the diffusion of conductive impurities, which affects the threshold voltage and parasitic resistance, and existing solutions do not effectively manage this diffusion without increasing parasitic resistance.

Innovation Solution

A semiconductor device design that includes a diffusion restraining layer in contact with the side surfaces of the source/drain extension regions but not the bottom surfaces, using impurities like C to prevent horizontal diffusion of conductive impurities such as B or As, thereby reducing short channel effects without increasing parasitic resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If diffusion restraining layer is formed to prevent conductive impurity diffusion, then short channel effect is reduced, but parasitic resistance increases

Engineering Contradiction:

Improveshort channel effect controlVSAvoidparasitic resistance

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The diffusion restraining layer is selectively formed only on the side surfaces of the extension regions, not on the bottom surfaces. This local application prevents conductive impurity diffusion in the lateral direction while avoiding interference with vertical carrier transport, thus reducing short channel effect without significantly increasing parasitic resistance.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The diffusion restraining layer is divided into multiple discrete regions positioned at specific locations where impurity diffusion needs to be controlled. By segmenting the restraining layer structure and positioning it only where needed on side surfaces, the patent achieves effective impurity confinement while minimizing overall resistance impact.

Inventive Principle:

Principle #1Segmentation

2Reliability

If diffusion restraining layer contacts bottom surface of extension region, then impurity diffusion is suppressed, but carrier transport is hindered

Engineering Contradiction:

Improveimpurity diffusion controlVSAvoidcarrier transport resistance

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively suppresses horizontal diffusion of conductive impurities, reducing short channel effects and maintaining sufficient depth of the extension regions, thus minimizing parasitic resistance and improving transistor performance.

Implementation Method 1

configured to prevent a diffusion of the conductive impurity in the source region

Methodology Applied

Scientific EffectDiffusion: Diffusion

Implementation Method 2

including an impurity other than the conductive impurity

Methodology Applied

Scientific EffectImpurity segregation:

Data Source

PatentUS8154077B2Semiconductor device

Publication Date: 2012.04.10 KIOXIA CORP

AI summary

According to an embodiment, a semiconductor device includes a gate electrode formed on a semiconductor substrate via an insulating layer; a source region including an extension region, a drain region including an extension region, a first diffusion restraining layer configured to prevent a diffusion of the conductive impurity in the source region and including an impurity other than the conductive impurity, and a second diffusion restraining layer configured to prevent a diffusion of the impurity in the drain region and including the impurity other than the conductive impurity.