Semiconductor Device Digital Analog Circuit Separation
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Solution Overview
Problem
Semiconductor devices with both digital and analog circuits face challenges in achieving low power consumption and reducing noise interference, as miniaturization leads to increased power consumption and 1/f noise, and halo implantation affects threshold voltage and noise levels.
Innovation Solution
A manufacturing method that separates digital and analog circuit areas on a semiconductor substrate using element separation layers, forming distinct well layers and gate electrodes, and implementing different impurity implantation techniques to control impurity concentration and reduce transient enhanced diffusion (TED) and 1/f noise, including shallower source and drain regions in analog circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If miniaturization of MOS transistor is performed to achieve high speed and high density, then device density and speed are improved, but power consumption increases rapidly due to short-channel effect
Solution Approach 1:
The patent applies different impurity concentration profiles to different regions: high impurity concentration at source/drain ends (halo implantation) to suppress short-channel effect and reduce power consumption, while maintaining lower impurity concentration in the channel region to preserve high-speed performance. This local differentiation resolves the contradiction between power consumption and device performance.
2Use of energy by moving object
If halo implantation is performed to suppress short-channel effect and reduce power consumption, then power consumption is improved, but 1/f noise increases in analog circuits
Solution Approach 1:
The patent segments the wafer into digital circuit areas and analog circuit areas, applying different impurity implantation strategies to each. Digital circuits receive standard halo implantation for low power consumption, while analog circuits receive reduced or no halo implantation to minimize 1/f noise. This spatial segmentation resolves the contradiction between power consumption and noise performance.
3Object-generated harmful factors
If channel length is increased to reduce 1/f noise in analog circuits, then noise performance is improved, but device area increases and leakage current becomes problematic
Solution Approach 1:
The patent changes the impurity concentration parameter in analog circuits by reducing or eliminating halo implantation, which suppresses 1/f noise without requiring increased channel length. This allows maintaining compact device area while achieving low noise performance through parameter optimization rather than geometric scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables low power consumption in digital circuits and reduced noise interference in analog circuits by controlling impurity concentration and TED, maintaining high-speed and high-density performance.
Implementation Method 1
forming a first well layer by implanting impurities of a first conductivity type into a digital circuit forming area of the semiconductor substrate; forming a second well layer by implanting impurities of the first conductivity type into an analog circuit forming area
Implementation Method 2
controlling impurity concentration and reduce transient enhanced diffusion (TED)
Data Source
AI summary
An object of the present invention is to provide a semiconductor device and a manufacturing method thereof that may achieve low power consumption in a digital circuit and reduce influence of noise in an analog circuit. The manufacturing method of the semiconductor device includes a first source/drain forming step of forming a first source region and a first drain region by implanting impurities of a second conductivity type into a digital side second conductivity type impurity layer using a gate electrode and a sidewall as a mask and a second drain/source forming step of forming a second source region and a second drain region by implanting impurities of the second conductivity type into an analog side second conductivity type impurity layer using a gate electrode and a sidewall as a mask more shallowly than the impurities of the second conductivity type implanted in the first source/drain forming step.