Semiconductor Timing Generator Using Segmented Digital Delay Control
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Solution Overview
Problem
As semiconductor devices, such as DRAMs, miniaturize, variations in device characteristics like threshold voltage and leakage current increase, leading to timing errors and reduced yield due to variations in delay times of analog delay circuits, which are not effectively managed by conventional analog delay circuits, especially under changing voltage and temperature conditions.
Innovation Solution
A semiconductor device incorporating a timing generator that uses a combination of coarse and fine delay circuits, driven by multiple clock signals, to precisely control timing signals, reducing variations and improving access time while minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If memory cell miniaturization is advanced to reduce parasitic capacitances and achieve low voltage operation, then power consumption is reduced and operating speed is improved, but device characteristic variations increase causing timing errors and yield reduction
Solution Approach 1:
The delay circuit is segmented into multiple stages (first delay circuit, second delay circuit, third delay circuit) with different delay characteristics. Each stage contributes differently to the total delay, allowing the system to achieve stable timing control by combining multiple segmented delay elements rather than relying on a single analog delay circuit that is sensitive to process variations.
Solution Approach 2:
The invention changes the parameter of delay control from continuous analog adjustment to discrete digital control. By using digital control signals to select predetermined delay times, the system achieves stable and accurate timing control that is not affected by process variations, voltage changes, or temperature fluctuations that plague analog delay circuits.
2Adaptability or versatility
If analog delay circuits are used for timing control, then timing adjustment is flexible, but timing variations occur due to device characteristic variations and environmental changes
Solution Approach 1:
The delay circuit is designed to operate in two distinct modes: a first operation mode where the first delay circuit is active for larger delay adjustments, and a second operation mode where the second delay circuit is active for finer delay adjustments. This dynamic switching between different delay circuit configurations allows the system to maintain both flexibility and precision across different timing requirements.
Solution Approach 2:
The invention replaces the mechanical/analog delay adjustment mechanism with a digital control system. Instead of using analog components whose delay characteristics drift with environmental changes, the system uses digital control signals to selectively activate different delay circuit paths, providing stable and precise timing control that is immune to process and environmental variations.
3Manufacturing precision
If multiple delay circuits are combined to reduce timing variations, then timing precision is improved, but device complexity increases
Solution Approach 1:
Multiple delay circuits with different delay characteristics are merged into a unified delay control system. The first delay circuit, second delay circuit, and third delay circuit are combined and controlled by a single digital control signal that can selectively activate different delay paths, achieving precise timing control without requiring separate independent control mechanisms for each delay element.
Solution Approach 2:
The delay control system is designed with multi-functionality to handle different timing requirements using a single unified architecture. The same delay control circuit can provide different delay amounts by selectively activating different delay circuit paths based on the digital control signal, eliminating the need for multiple separate delay control systems and reducing overall complexity.
Data Source
AI summary
Disclosed is a semiconductor device including a first clock generator that generates a first clock signal having a first period from an input clock signal, a second clock generator that generates a second clock signal having a second period from the input clock signal, and a timing generator that receives the first clock signal, the second clock signal, an activation signal from a command decoder and a selection signal for selecting the delay time from a timing register to produce a timing signal delayed as from activation of the activation signal by a delay equal to a sum of a time equal to a preset number m prescribed by the selection signal times the first period and a time equal to another preset number n prescribed by the selection signal times the second period. The timing register holds the values of m and n. These values are set in the timing register in an initialization sequence at the time of a mode register set command. In the operating states, the timing signals are output from the timing generator at a desired timing based on the information stored in the timing register (FIG. 6).