Multi-State Semiconductor Diode Memory Cell for Leakage Reduction
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Solution Overview
Problem
Current nonvolatile memory arrays face challenges in achieving erasable or multi-state memory cells using conventional semiconductor materials, particularly in scaling to small sizes and reducing leakage current in dense cross-point arrays.
Innovation Solution
The development of a memory cell using a polycrystalline semiconductor diode with a dielectric rupture antifuse, configured to achieve multiple resistivity states through electrical pulses, allowing for both one-time programmable and rewritable operations by utilizing forward and reverse biasing schemes to minimize leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional semiconductor materials are used for nonvolatile memory cells, then fabrication is simpler, but achieving erasable or multi-state cells at small dimensions is difficult
Solution Approach 1:
The patent changes the electrical parameters (voltage polarity, current direction) applied to the semiconductor diode to achieve different resistivity states. By applying forward bias, reverse bias, and controlled current pulses, the diode transitions between high and low resistivity states, enabling multi-state memory operation using conventional semiconductor materials
Solution Approach 2:
The patent employs periodic electrical pulses with specific timing and duration to program and erase memory cells. Controlled current pulses are applied in sequences to transition the diode between states, with pulse width and amplitude carefully managed to achieve reliable multi-state operation without damaging the conventional semiconductor structure
2Productivity
If memory arrays are scaled to small dimensions, then density increases, but leakage current becomes problematic
Solution Approach 1:
The patent uses selective biasing schemes where word lines and bit lines are maintained at specific potentials to minimize voltage across unselected cells. By keeping unselected cells at equipotential or near-equipotential conditions, leakage current paths are suppressed while still enabling access to selected cells through controlled potential differences
3Adaptability or versatility
If floating gate or SONOS memory cells are used, then erasable and multi-state functionality is achieved, but device complexity and fabrication difficulty increase
Solution Approach 1:
The patent extracts the complex floating gate or charge trapping structures from the memory cell design and replaces them with a simple semiconductor diode. The multi-state capability is achieved not through complex physical structures but through controlled electrical manipulation of the diode's resistivity, thereby simplifying the device while maintaining functionality
Solution Approach 2:
The semiconductor diode serves multiple functions: it acts as the memory element, the switching device, and the resistivity control mechanism all in one component. This universal use of the diode eliminates the need for separate transistors, charge storage layers, and control structures required in conventional memory cells
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the creation of memory cells with multiple data states, reducing leakage current and allowing for scalable, dense memory arrays with flexible programming capabilities, enhancing the efficiency and versatility of nonvolatile memory technology.
Implementation Method 1
a memory element comprising a semiconductor material configurable to one of at least three resistivity states
Implementation Method 2
configured to achieve multiple resistivity states through electrical pulses, allowing for both one-time programmable and rewritable operations
Implementation Method 3
utilizing forward and reverse biasing schemes to minimize leakage current
Data Source
AI summary
A method for using a multi-use memory cell and memory array are disclosed. In one preferred embodiment, a memory cell is operable as a one-time programmable memory cell or a rewritable memory cell. The memory cell comprises a memory element comprising a semiconductor material configurable to one of at least three resistivity states, wherein a first resistivity state is used to represent a data state of the memory cell when the memory cell operates as a one-time programmable memory cell but not when the memory cell operates as a rewritable memory cell. A memory array with such memory cells is also disclosed. In another preferred embodiment, a memory cell is provided comprising a switchable resistance material, wherein the memory cell is operable in a first mode in which the memory cell is programmed with a forward bias and a second mode in which the memory cell is programmed with a reverse bias.