Semiconductor Device with Direct Leadframe Attachment
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Solution Overview
Problem
Conventional DC-DC converters have significant height and electrical parasitic issues due to the use of metallic clips, which introduce inductance and resistance, and pose risks of wire sweep and electrical shorts during encapsulation.
Innovation Solution
The solution involves eliminating clips by assembling sync and control FET chips side-by-side in a pre-coined recess of the leadframe pad, allowing direct attachment to a circuit board, which reduces parasitic resistances and inductances and enhances thermal dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metallic clips are used to connect FET chips and provide electrical connections, then the mechanical strength and electrical connectivity are improved, but the parasitic inductance and resistance increase, and the device height increases
Solution Approach 1:
The patent removes the metallic clips from the assembly, extracting the harmful parasitic inductance and resistance sources while maintaining electrical connectivity through direct leadframe connections. The clips are completely eliminated from the design, replacing them with a integrated leadframe structure that provides both mechanical support and electrical pathways without intermediate connection elements.
Solution Approach 2:
The patent merges the mechanical support function and electrical connection function into a single integrated leadframe structure. The leadframe simultaneously provides the mechanical platform for mounting FET chips and the electrical pathways for current flow, eliminating the need for separate clip components and reducing overall parasitic effects.
2Device complexity
If metallic clips are used to assemble FET chips vertically, then the assembly structure is simplified, but the wire sweep risk and electrical short risk during encapsulation increase
Solution Approach 1:
The patent extracts and removes the clips that cause wire sweep and electrical short risks during encapsulation. By eliminating these protruding metallic components, the risk of wires contacting clips during the molding process is completely removed, ensuring reliable encapsulation without short circuits.
3Reliability
If FET chips are assembled with clips in a conventional configuration, then the electrical connections are established, but the thermal dissipation efficiency decreases due to increased thermal resistance
Solution Approach 1:
The patent merges the electrical connection pathway and thermal conduction pathway into a single direct interface between the FET chip and leadframe. This integrated connection provides both electrical connectivity and efficient thermal conduction simultaneously, allowing heat to flow directly from the chip through the leadframe without the thermal resistance introduced by clip intermediaries.
4Strength
If conventional packaging with clips is used, then the assembly is mechanically robust, but the height of the converter increases
Solution Approach 1:
The patent extracts and removes the height-contributing clip components from the assembly. By eliminating these vertical protrusions, the overall converter height is significantly reduced while the leadframe provides sufficient mechanical support to maintain structural robustness without the clips.
Data Source
AI summary
Disclosed embodiments relate to a semiconductor device. A semiconductor device is fabricated by attachment of a first chip to a first surface of a pad of a leadframe. Each of one or more terminals of the first chip is connected to a respective lead of the leadframe. The first chip and the first surface of the pad are then encapsulated in a packaging material, while leaving an opposite second surface of the pad exposed. A second chip is attached to a recessed portion of the second surface of the pad so that at least one terminal of the second chip is substantially coplanar with an un-recessed portion of the second surface. In one embodiment, a third chip is also attached to the recessed portion of the second surface so that at least one terminal of the third chip is substantially coplanar with the un-recessed portion of the second surface.