Semiconductor Interconnect Structure With Direct Plug Contact
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Solution Overview
Problem
The existing semiconductor manufacturing processes exhibit high contact resistance between conductive plugs and metal interconnect layers, which degrades the electrical connection performance and worsens with decreasing feature sizes.
Innovation Solution
A semiconductor structure and method that omits the adhesion layer between the conductive plug and the bottom interconnect layer by ensuring direct contact between the conductive plug's bottom and the bottom interconnect layer, and between the conductive plug's sidewall and the top dielectric layer, using materials like Co, W, Ru, and Ti for improved conductivity and reduced resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If an adhesion layer is formed between the conductive plug and the bottom interconnect layer, then adhesion strength is improved, but contact resistance increases
Solution Approach 1:
The patent removes the adhesion layer from the interface between the conductive plug and the bottom interconnect layer, extracting the harmful element that caused high contact resistance. The adhesion layer is retained only where needed (between top interconnect layer and top dielectric layer) to maintain adhesion strength while eliminating its negative impact on electrical contact.
Solution Approach 2:
The patent applies different structural configurations to different regions: the adhesion layer is present between the top interconnect layer and top dielectric layer where adhesion is needed, but absent between the conductive plug and bottom interconnect layer where direct electrical contact is required. This localized differentiation resolves the contradiction by providing adhesion only where necessary.
2Reliability
If the conductive plug volume is increased to reduce resistance, then electrical connection performance is improved, but device complexity increases
Solution Approach 1:
The patent extends the conductive plug in the vertical dimension by having it protrude through the top dielectric layer, increasing its volume and cross-sectional area for current flow. This dimensional extension improves electrical connection performance without requiring lateral expansion that would increase device footprint and complexity.
Data Source
AI summary
Semiconductor structures and methods for forming the same are provided. In one form, a semiconductor structure includes: a substrate; a bottom dielectric layer, located on the substrate; a bottom interconnect layer, located in the bottom dielectric layer; a top dielectric layer, located on the bottom dielectric layer and the bottom interconnect layer; a conductive plug, located in the top dielectric layer on a top of the bottom interconnect layer and having a bottom in direct contact with the bottom interconnect layer and a sidewall in direct contact with the top dielectric layer; a top interconnect layer, located in the top dielectric layer above the conductive plug and in contact with the conductive plug; and a top adhesion layer, located between the top interconnect layer and the top dielectric layer. By means of embodiments and implementations of the present disclosure, electrical connection performance of a semiconductor structure is optimized.