Semiconductor Patterning with Directional Opening Expansion
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Solution Overview
Problem
The resolution limitations of EUV lithography in semiconductor manufacturing at 7 nm or smaller nodes require expensive double-patterning technology, and overlay error tolerance becomes smaller as pitch or CD of the pattern becomes smaller.
Innovation Solution
A directional etching and deposition technique is employed to modify the dimensions of openings in semiconductor manufacturing, specifically using directional processes with controlled ion beams and plasma etching to enlarge openings in one direction while minimizing changes in the perpendicular direction, thereby compensating for overlay errors and improving process margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If EUV lithography with double-patterning technology is employed to achieve smaller L/S pitch patterns, then the pattern resolution is improved, but the manufacturing cost increases significantly
Solution Approach 1:
The patent divides the patterning process into two separate steps: first forming a preliminary pattern, then using directional etching to selectively enlarge openings in specific regions. This segmentation allows achieving high resolution patterns without requiring expensive double-patterning lithography, as the directional etching step creates the final fine features from a coarser initial pattern
Solution Approach 2:
The patent replaces the mechanical/optical lithography system (EUV) with a directional etching process that uses plasma and ion beams to physically modify the pattern. Instead of relying on lithographic resolution to define final dimensions, the invention uses controlled material removal to achieve precise pattern features, substituting a cheaper lithography step with a more selective etching process
2Manufacturing precision
If the pitch or CD of the pattern becomes smaller to achieve higher resolution, then the pattern detail is improved, but the overlay error tolerance becomes smaller
Solution Approach 1:
The patent applies preliminary anti-action by performing directional etching to selectively enlarge openings before subsequent lithography steps. This pre-compensates for expected overlay errors by creating larger openings that can tolerate misalignment better, while still achieving the required final pattern dimensions after the second lithography exposure
Solution Approach 2:
The patent changes the dimensional parameters of openings dynamically through directional etching, enlarging them in specific directions based on process requirements. This parameter modification allows the openings to have different effective sizes in different orientations, providing tolerance for overlay errors while maintaining the required pattern resolution
3Ease of operation
If conventional isotropic etching is used to modify openings, then the process is simple, but the opening dimensions change uniformly in all directions causing overlay errors
Solution Approach 1:
The patent introduces asymmetry into the etching process by using directional etching that selectively enlarges openings in specific directions rather than uniformly in all directions. This asymmetric modification allows precise control over opening dimensions, enabling compensation for overlay errors while maintaining relative process simplicity through a single etching step
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This technique enhances the manufacturing yield by compensating for overlay errors and reducing the need for costly double-patterning, achieving precise pattern formation with improved resolution and tolerance.
Implementation Method 1
directional processes with controlled ion beams and plasma etching to enlarge openings
Implementation Method 2
directional processes with controlled ion beams and plasma etching to enlarge openings
Data Source
AI summary
In a method of manufacturing a semiconductor device, a target layer to be patterned is formed over a substrate, a mask layer having an opening is formed over the target layer, the opening is enlarged in a first direction without enlarging the opening in a second direction crossing the first direction by a directional process, where the first and second directions are parallel to an upper surface of the substrate, and the target layer is patterned to form a hole corresponding to the opening.


