Semiconductor Integrated Circuit with Programmable DMA Access Control
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Solution Overview
Problem
Current data transfer schemes in semiconductor integrated circuits, such as SoC, face issues like CPU resource consumption, complex DMA controller specifications, prolonged development periods, and difficulties in satisfying processing speed performance due to hardware complexity and limited recyclable parts, especially when implementing Quality of Service (QoS) mechanisms.
Innovation Solution
A semiconductor integrated circuit design that includes a bus, memory, an arithmetic processing unit, a first DMA controller, and functional blocks with a second DMA controller and an access condition setting unit to manage data transfer between memory and functional macros, allowing flexible QoS control through programmable DMA transfers and reducing hardware complexity by using software-controlled access conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CPU controls data transfer between functional macros, then data transfer can be performed, but CPU resource is consumed and the main process is prevented
Solution Approach 1:
The patent introduces a DMA controller as an intermediary device between the CPU and functional macros. The DMA controller handles data transfer operations independently, allowing the CPU to initiate transfers and then continue its main processing without being blocked. The DMA controller mediates the data movement between memory and functional macros, eliminating the need for CPU intervention during transfer operations.
2Productivity
If DMA controller connected to system bus controls data transfer between multiple functional macros, then data transfer is enabled, but specification becomes complicated and development period is prolonged
Solution Approach 1:
The patent divides the DMA control functionality into separate units, with each functional macro having its own dedicated DMA controller. This segmentation allows each DMA controller to have a simplified, standardized specification rather than one complex controller handling all functional macros. The system is divided into independent data transfer paths, each with its own simple DMA controller.
Solution Approach 2:
The patent creates a universal DMA controller design that can be replicated for each functional macro. Instead of designing a complex controller that handles all macros, a standardized DMA controller unit is designed once and then instantiated multiple times, one for each functional macro. This multi-functional approach reduces development complexity and time.
3Adaptability or versatility
If QoS mechanism is implemented in DMA controller, then priority control between processes is achieved, but hardware becomes more complicated and processing speed performance is difficult to satisfy
Solution Approach 1:
The patent introduces an access condition setting unit as an intermediary that manages priority control externally to the DMA controller hardware. Instead of embedding complex QoS mechanisms within the DMA controller itself, the system uses separate access condition setting units that configure DMA transfer priorities through software or configuration registers. This keeps the DMA controller hardware simple while still enabling priority control functionality.
4Productivity
If DMA transfer specification is determined at SoC specification stage, then data transfer control is established, but development period is prolonged and recyclability is reduced
Solution Approach 1:
The patent makes the DMA transfer specification dynamic and configurable rather than fixed at the SoC design stage. The access condition setting units allow transfer parameters, priorities, and configurations to be modified at runtime or during system initialization. This dynamic approach enables the same hardware to adapt to different application requirements without requiring redesign, thereby reducing development time for new products.
Solution Approach 2:
The patent enables modification of DMA transfer parameters such as transfer size, priority levels, and access conditions without changing the hardware architecture. By making these parameters configurable through software or configuration registers, the system can be adapted to different applications and requirements, improving recyclability while reducing development time for new product variants.
Data Source
AI summary
A semiconductor integrated circuit includes a bus, a memory connected to the bus, an arithmetic processing unit connected to the bus, a first DMA controller connected to the bus, and at least one functional block connected to the bus. The functional block includes a functional macro which is configured to perform a process that realizes a given function, a second DMA controller which is configured to control data transfer between the memory and the functional macro, and an access condition setting unit which is configured to set an access condition regarding the DMA transfer between the memory and the functional macro.