Semiconductor Domain Crossing Circuit for Clock Frequency Mismatch
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Solution Overview
Problem
Semiconductor apparatuses face issues with signal reception when clock signals on the transmitter and receiver sides have different frequencies, leading to metastable states and impaired normal operation due to frequency differences.
Innovation Solution
Incorporating a semiconductor apparatus with a domain crossing function that includes storage units and an edge detection circuit to synchronize and process signals across different clock frequencies, reducing latency and preventing metastable states by latching and generating data at specific edges of the clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If clock signals on transmitter and receiver sides have different frequencies, then the semiconductor apparatus can operate in different clock domains, but the receiver cannot correctly recognize signals due to metastable states
Solution Approach 1:
The receiver is divided into multiple storage units (first storage unit, second storage unit) that operate at different clock edges. The first storage unit samples data on the first clock edge, while the second storage unit samples on the second clock edge, segmenting the sampling process to handle frequency differences between clock domains
Solution Approach 2:
The first storage unit acts as an intermediary between the transmitter and second storage unit. It receives data synchronized to the first clock signal and converts it to be synchronized with the second clock signal, mediating the frequency difference between the two clock domains to prevent metastable states
2Device complexity
If traditional single storage unit is used for clock domain crossing, then device complexity is low, but signal synchronization fails when clock frequencies differ
Solution Approach 1:
The single storage unit is segmented into multiple storage units (first storage unit with first output, second storage unit with second output), each handling different clock edges. This segmentation enables proper synchronization across clock domains while maintaining a relatively simple overall structure
Solution Approach 2:
The system dynamically selects which clock edge (first or second) to use for sampling based on the operational requirements. The storage units are configured to respond to different edges of the clock signal, providing dynamic adaptability to handle frequency differences without requiring complex frequency translation circuits
Data Source
AI summary
A semiconductor apparatus may include a first semiconductor apparatus configured to transmit a first input signal as first data in synchronization with a first edge of a first clock signal having a first frequency. The semiconductor apparatus may also include a second semiconductor apparatus including: a first storage unit, configured to receive the first data as a set signal and output a second input signal as an internal signal in synchronization with a first edge of a second clock signal having a second frequency; and a second storage unit, configured to output the internal signal as second data in synchronization with a second edge of the second clock signal.