3D Semiconductor Device with Doped Junctions
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Solution Overview
Problem
Current semiconductor devices with three-dimensional structures face challenges in achieving structural stability and operational reliability, particularly in manufacturing processes that result in defects and unpredictable outcomes.
Innovation Solution
A semiconductor device with a three-dimensional structure is designed, featuring a substrate, alternately stacked first and second electrode lines, and doped semiconductor layer patterns that form pnpn or npnp junctions, allowing for the fabrication of thyristor-type memory devices with minimal defects through selective epitaxial growth and ion etch-free metal electrode formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional three-dimensional semiconductor structures are manufactured, then device integration is achieved, but structural stability and operational reliability deteriorate due to manufacturing defects
Solution Approach 1:
The device pattern is segmented into multiple doped semiconductor layer patterns (first doped semiconductor layer pattern, second doped semiconductor layer pattern, third doped semiconductor layer pattern) with different doping types and concentrations. This segmentation allows each layer to perform specific functions in the pnpn or npnp junction, improving structural stability and reducing manufacturing defects while maintaining high device integration
Solution Approach 2:
Different regions of the semiconductor structure are assigned different doping types (n-type and p-type) and doping concentrations. The first doped semiconductor layer pattern has a first doping type and first doping concentration, while the second has a second doping type and second doping concentration. This local quality variation enables precise control of electrical characteristics and improves operational reliability in each specific region of the device
2Ease of manufacture
If manufacturing processes are simplified to reduce defects, then ease of manufacture improves, but manufacturing precision deteriorates
Solution Approach 1:
The doped semiconductor layer patterns are formed with predetermined doping types and concentrations before final device assembly. The first doped semiconductor layer pattern, second doped semiconductor layer pattern, and third doped semiconductor layer pattern are prepared in advance with specific electrical characteristics, allowing subsequent assembly steps to proceed with higher ease of manufacture while maintaining manufacturing precision through pre-established layer quality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the structural stability and operational reliability of semiconductor devices by reducing defects and improving interface characteristics between doped semiconductor layers and electrodes, enabling efficient signal storage based on hysteresis characteristics.
Implementation Method 1
selective epitaxial growth
Implementation Method 2
hysteresis characteristics
Data Source
AI summary
A semiconductor device having a three-dimensional structure is disclosed herein. The semiconductor device includes a substrate. a first electrode line that extends in a first direction perpendicular to the substrate, a device pattern that extends from the first electrode line in a second direction parallel to the substrate, and a second electrode line connected to the device pattern. The device pattern may comprise at least one semiconductor layer pattern, where the at least one semiconductor layer pattern comprises an n-type dopant or a p-type dopant.