Semiconductor Doping Sequence for Lower Junction Leakage
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Solution Overview
Problem
As semiconductor devices integrate, the reduction in gate size increases series and contact resistances, leading to higher junction leakage currents and power consumption due to the proximity of metal silicide to the drain region edges, which existing manufacturing processes struggle to mitigate effectively.
Innovation Solution
A method involving multiple ion implantation and doping processes with precise mask patterns to form pre-amorphized, amorphized, and heavily-doped regions, accompanied by sidewall formation, reduces junction leakage by increasing the effective distance between the metal silicide and the drain region edge, thereby addressing the resistance and leakage issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If multiple ion implantation and doping processes with precise mask patterns are used to form pre-amorphized, amorphized, and heavily-doped regions, then junction leakage current is reduced, but device complexity and manufacturing process complexity increase
Solution Approach 1:
The doping process is divided into multiple sequential stages: first ion implantation to form pre-amorphized regions, second ion implantation to form amorphized regions, and multiple doping processes to form heavily-doped source and drain regions. Each stage uses specific mask patterns (first mask pattern, second mask pattern, third mask pattern) to precisely control the doping regions, thereby reducing junction leakage current through controlled distance between metal silicide and drain region edge
Solution Approach 2:
Before the final doping process, the method performs preliminary ion implantation to create pre-amorphized regions, followed by second ion implantation to create amorphized regions. These preliminary actions modify the crystal structure and prepare the regions for subsequent doping, ensuring precise control over dopant distribution and reducing junction leakage current
2Productivity
If feature size of gate is reduced to increase integration degree, then device integration increases, but distance between metal silicide and drain region edge decreases causing increased junction leakage current
Solution Approach 1:
The method applies different doping concentrations and types to different local regions: lightly-doped regions are formed first, followed by heavily-doped source and drain regions in specific areas. The mask patterns are designed to expose only the necessary regions for each doping step, creating local variations in doping that increase the effective distance between metal silicide and drain region edge, thereby reducing junction leakage current while maintaining small gate feature sizes
Solution Approach 2:
The method controls doping not only in the horizontal plane but also in the vertical dimension through multiple ion implantation steps at different energies and angles. By creating pre-amorphized and amorphized regions with specific depth profiles, the effective distance between metal silicide and drain region is increased in the vertical dimension, compensating for the reduced horizontal distance caused by smaller gate features
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces junction leakage currents and series resistances, enhancing the performance and power efficiency of semiconductor devices by optimizing the doping and silicide placement relative to the gate structure.
Implementation Method 1
implanting first ions into the preset source region and the preset drain region by taking the first mask pattern as a first mask, to form pre-amorphized regions; implanting second ions into the pre-amorphized regions to form amorphized regions
Implementation Method 2
thermal treatment is performed to make the metal layer react with silicon in the active region and the polysilicon gate, so as to form a metal silicide on surfaces of the active region and the polysilicon gate
Data Source
AI summary
A method for manufacturing a semiconductor device, including: acquiring a substrate, wherein a gate structure is formed on the substrate; implanting first ions into the substrate to form pre-amorphized regions at two sides of the gate structure respectively; implanting second ions into the pre-amorphized regions to form amorphized regions in the pre-amorphized regions respectively; forming first sidewalls each at a respective one of the two sides of the gate structure; performing a second doping process to form first doped regions in the amorphized regions; forming second sidewalls each at a side of a respective first sidewall; and forming a heavily-doped source region and a heavily-doped drain region in the first doped regions respectively.