Semiconductor Doping Sequence for Reduced Random Dopant Fluctuation
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Solution Overview
Problem
Nano-scaled semiconductor devices face issues with random dopant fluctuation, leading to variability in device characteristics due to the decreased size of transistors and increased impact of individual dopant atoms.
Innovation Solution
A semiconductor device manufacturing method that includes performing a well implant process and a source/drain implant process on a broad region of the substrate before defining active areas or forming shallow trench isolations, followed by a two-step annealing process with different temperatures to activate dopants and relieve stress, thereby improving dopant distribution and reducing random dopant fluctuation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is scaled down for cost reduction and high volume manufacturing, then productivity and cost efficiency are improved, but random dopant fluctuation increases leading to device variability
Solution Approach 1:
The patent performs the dopant implant process on the entire substrate region before defining active areas or forming shallow trench isolations. This preliminary action allows dopants to be distributed uniformly across the substrate before any segmentation or isolation structures are created, preventing random dopant fluctuation that would occur if implantation were performed after active area definition.
Solution Approach 2:
The patent implements a two-step annealing process with different temperatures: a first annealing step at a lower temperature for shallow-trench-isolation annealing, and a second annealing step at a higher temperature for dopant-activation annealing. This localized quality approach optimizes each annealing step for its specific purpose, ensuring both isolation quality and dopant activation while maintaining uniform dopant distribution.
2Manufacturing precision
If dopant implant process is performed after defining active areas and forming shallow trench isolations, then manufacturing precision is improved, but random dopant fluctuation increases
Solution Approach 1:
The patent reverses the conventional sequence by performing dopant implantation on the broad substrate region before defining active areas or forming shallow trench isolations. This preliminary action ensures that dopants are distributed uniformly across the entire region, and subsequent definition of active areas and formation of isolations do not disrupt this uniform distribution, thereby eliminating random dopant fluctuation.
3Device complexity
If a single annealing process is used, then device complexity is reduced, but dopant activation and stress relief are insufficient
Solution Approach 1:
The patent divides the annealing process into two distinct steps: a first annealing step at a lower temperature specifically for shallow-trench-isolation annealing, and a second annealing step at a higher temperature for dopant-activation annealing. This segmentation allows each annealing step to be optimized for its specific function, ensuring both isolation quality and complete dopant activation without compromising the other.
Solution Approach 2:
The patent employs different temperature parameters for the two annealing steps. The first annealing step uses a lower temperature suitable for isolation annealing, while the second annealing step uses a higher temperature necessary for effective dopant activation. This parameter change strategy ensures that each process step operates at its optimal temperature, achieving both isolation and dopant activation objectives.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in improved dopant distribution and reduced random dopant fluctuation, leading to enhanced device reliability and performance by optimizing the distribution of dopant atoms within the semiconductor material.
Implementation Method 1
performing an annealing process to the region of the substrate
Implementation Method 2
the annealing process includes a first annealing step using a first annealing temperature and a second annealing step using a second annealing temperature
Implementation Method 3
performing a well implant process on a region of a substrate; performing a source/drain implant process on the region of the substrate
Data Source
AI summary
A semiconductor device manufacturing method includes the following steps. A well implant process is performed on a region of a substrate. A source/drain implant process is performed on the region of the substrate. An active area is defined on the region of the substrate. Shallow trench isolations are formed in the active area. An annealing process is performed to the region of the substrate.