Semiconductor Double Patterning with Sharp Corner Sidewalls
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Solution Overview
Problem
Current double patterning technologies face challenges in forming fine patterns with different widths, leading to convexly-curved sidewalls and steep slopes, which complicates the patterning of underlying layers and results in undesired pattern profiles.
Innovation Solution
A method involving the sequential formation of sacrificial patterns, spacers, and upper patterns on a substrate, followed by selective removal and etching processes, allows for the formation of buffer and upper patterns with varying widths, enabling the creation of fine patterns with sharp corners and different widths using the upper patterns as etch masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional double patterning technology is used to form fine patterns, then pattern dimension can be reduced below minimum feature size, but the sidewalls become convexly-curved with steep slopes, complicating subsequent patterning
Solution Approach 1:
The patent segments the patterning process into multiple distinct stages: forming sacrificial patterns, depositing spacers, selectively removing sacrificial patterns, and forming upper patterns. This segmentation allows each stage to be optimized independently, producing patterns with sharp corners and controlled sidewall profiles rather than convexly-curved shapes
Solution Approach 2:
The patent performs preliminary actions by forming sacrificial patterns first, then depositing spacers on their sidewalls before removing the sacrificial patterns. This preliminary spacer formation establishes the final pattern geometry early in the process, ensuring sharp corners and controlled sidewall slopes are achieved before subsequent etching operations
2Manufacturing precision
If conventional double patterning is used, then fine patterns can be formed, but the steep slopes and convexly-curved sidewalls result in undesired pattern profiles for underlying layers
Solution Approach 1:
The patent introduces a vertical dimension by forming upper patterns that extend above the buffer layer. These upper patterns serve as etch masks for patterning the buffer layer and underlying structures. The elevated position and sharp geometry of upper patterns improve mask effectiveness and simplify the patterning of underlying layers compared to conventional approaches
3Productivity
If double patterning technology is used to form fine patterns, then highly-integrated semiconductor devices can be realized, but forming patterns with different widths becomes necessary and complex
Solution Approach 1:
The patent applies local quality by forming different types of spacers (first spacers and second spacers) with different properties in different regions. First spacers are formed on first sacrificial patterns and second spacers on second sacrificial patterns, allowing each region to have customized pattern widths. This enables efficient formation of patterns with different widths without significantly increasing process complexity
Data Source
AI summary
Provided is a method of fabricating a semiconductor device. In the method, a double patterning technology is used to form various patterns with different widths.