Semiconductor Drain Region Segmentation for ESD Protection

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Solution Overview

Problem

Integrated chips (ICs) are susceptible to damage from electrostatic discharge (ESD) pulses, which can cause catastrophic damage to semiconductor devices, particularly in open-drain buffer circuits, and existing solutions do not provide sufficient ESD protection to meet specifications for HBM ESD class 2 and greater devices.

Innovation Solution

The IC design incorporates a semiconductor device with a drain region comprising multiple first doped regions and second doped regions, where the first doped regions have a higher doping concentration and are spaced to create a high resistance across the drain region, reducing the voltage spike and preventing damage to the gate dielectric during ESD events.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the drain region uses a single doped region with uniform doping concentration, then the device structure is simple and manufacturing is easier, but the ESD protection capability is insufficient

Engineering Contradiction:
ImproveESD protection capabilityVSAvoiddrain region structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The drain region is segmented into multiple first doped regions and second doped regions with alternating doping concentrations. This segmentation creates a multi-layered structure that provides progressive resistance to ESD pulses, allowing the device to withstand higher voltage spikes while maintaining controlled current flow during normal operation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the drain are assigned different doping concentrations to serve different functions. The first doped regions with higher concentration provide ESD protection by creating high resistance paths, while the second doped regions with lower concentration maintain low resistance for normal device operation. This local differentiation optimizes both protection and performance.

Inventive Principle:
Principle #3Local quality

2Productivity

If the doping concentration in the drain region is increased to reduce resistance and improve current flow, then device performance during normal operation improves, but the ESD protection capability deteriorates due to lower voltage spike resistance

Engineering Contradiction:
Improvecurrent flow capabilityVSAvoidESD protection capability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The drain region is divided into alternating high-concentration and low-concentration doped regions. During normal operation, current flows through the low-resistance paths provided by the second doped regions. During ESD events, the high-concentration first doped regions activate to provide high resistance and limit current, thus protecting the device.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The drain region exhibits dynamic resistance characteristics that adapt to operating conditions. Under normal low-voltage operation, the structure presents low resistance for efficient current flow. Under high-voltage ESD stress, the high-concentration regions dominate to provide high resistance and limit damage, effectively switching between protection and performance modes.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances ESD protection, allowing the IC to withstand ESD pulses exceeding 2,000 V, meeting or exceeding specifications for HBM ESD class 2 and greater devices, thereby preventing damage to the semiconductor device.

Implementation Method 1

The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Data Source

PatentUS11393809B2Semiconductor device having improved electrostatic discharge protection
Publication Date: 2022.07.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11393809B2 patent drawing
  • US11393809B2 patent drawing
  • US11393809B2 patent drawing

AI summary

Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.