Semiconductor Drift Layer with Depletion-Extension Regions
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Solution Overview
Problem
Conventional semiconductor devices face challenges in miniaturization due to increased on-resistance caused by narrow connection regions between field relaxation layers, which limits the ability to reduce the interval between opposing field relaxation layers and maintain high voltage withstand.
Innovation Solution
A semiconductor device structure featuring a drift layer with a reference concentration layer and a low concentration layer, along with depletion-layer extension regions that do not cover the side surfaces of the base regions, allowing for a wider interval between base regions without increasing on-resistance, and a method for manufacturing this device using specific impurity injection and thermal treatment processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the field relaxation layer covers the side surface of the base region to reduce field concentration, then the withstand voltage is improved, but the connection region width is narrowed causing increased on-resistance
Solution Approach 1:
The field relaxation layer is positioned only at the bottom surface of the base region rather than covering the side surface, changing the spatial dimension of coverage. This allows the connection regions to extend laterally with sufficient width while the field relaxation function is maintained at the bottom where the depletion layer originates, thus resolving the contradiction between withstand voltage and on-resistance
Solution Approach 2:
The field relaxation layer is applied selectively only at the bottom surface of the base region rather than uniformly across all surfaces. This local application provides field relaxation exactly where needed (at the depletion layer origin) while leaving the side surfaces available for wider connection regions, thereby maintaining both high withstand voltage and low on-resistance
2Volume of moving object
If the interval between opposing field relaxation layers is narrowed to enable miniaturization, then the device size is reduced, but the connection region width is further constrained increasing on-resistance
Solution Approach 1:
By relocating the field relaxation layer from side surface coverage to bottom surface-only coverage, the lateral space is freed up. This allows the connection regions to maintain adequate width even when the overall device interval is reduced, enabling miniaturization without sacrificing electrical performance
Solution Approach 2:
The field relaxation function is segmented to be performed only at the bottom surface rather than continuously along the side surface. This segmentation allows independent optimization of the connection region width in the lateral direction while maintaining field relaxation capability in the vertical direction, facilitating device miniaturization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor device achieves miniaturization while maintaining high voltage withstand by relaxing the electric field and preventing field concentration, thereby reducing on-resistance and enhancing withstand voltage without the need for extensive impurity diffusion.
Implementation Method 1
a pair of depletion-layer extension regions that are respectively provided in the reference concentration layer under diffusion layers of the base regions and include an impurity of the second conductive type at a concentration lower than the second reference concentration; Lower surfaces of the depletion-layer extension regions are deeper than a boundary between the low concentration layer and the reference concentration layer, and intrude into the low concentration layer
Implementation Method 2
a drift layer that includes a reference concentration layer including an impurity of a first conductive type at a first reference concentration and a low concentration layer provided under the reference concentration layer and including an impurity of the first conductive type at a concentration lower than the first reference concentration
Data Source
AI summary
A semiconductor device including a plurality of units having identical structures, each unit includes: a drain electrode; a drift layer that includes a low concentration layer on the drain electrode and a reference concentration layer on the low concentration layer, a gate electrode on the reference concentration layer; a pair of source regions that are provided on an upper surface of the reference concentration layer and in the vicinity of both ends of the gate electrode; a pair of base regions that surround outer surfaces of the source regions; a source electrode electrically connected to the source regions and the base regions; and a pair of depletion-layer extension regions that are respectively provided under the base regions in the reference concentration region. Boundaries between the depletion-layer extension regions and the low concentration layer are positioned lower than a boundary between the reference concentration layer and the low concentration layer.