Semiconductor Drift Region Voltage Blocking Optimization
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Solution Overview
Problem
Conventional power semiconductor devices face challenges in achieving high voltage blocking capability while maintaining low on-resistance and low output capacitance, as reducing on-resistance typically compromises voltage blocking capability.
Innovation Solution
The semiconductor device arrangement includes a first transistor with a drift region and a series connection of second transistors, where the second transistors are connected in series and parallel with the drift region of the first transistor, allowing for control terminal connections that adjust the voltage drop across the drift region to optimize on-resistance and voltage blocking capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If compensation regions or field plates are provided in the drift region to compensate doping charges, then the voltage blocking capability is maintained, but the device complexity increases
Solution Approach 1:
The patent extracts the voltage blocking function from the bulk drift region by creating a dedicated first drift region section with lower doping concentration. This allows the second drift region section to focus on reducing on-resistance without compromising voltage blocking, as the first section specifically handles the voltage blocking function. This separation eliminates the need for additional compensation regions or field plates.
Solution Approach 2:
The patent combines the voltage blocking function and the low-resistance conduction function into a single drift region structure with two sections. Instead of using separate compensation regions or field plates alongside the drift region, the drift region itself is structured to perform both functions through differential doping, thereby reducing device complexity while maintaining performance.
Data Source
AI summary
Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.