Resin-Sealed Semiconductor Device Thermal Stress Relief
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Solution Overview
Problem
In resin-sealed power semiconductor modules, the difference in linear expansion coefficients between ceramic insulating substrates and copper circuit patterns leads to stress and peeling issues, which can cause insulation failure and reduce the reliability of the module, especially under high temperatures.
Innovation Solution
The solution involves forming drill holes or annular grooves in the copper circuit patterns around the copper blocks, increasing their number or size towards the outside, which reduces the average volume of the conductive film, thereby alleviating thermal stress and improving adhesion of the sealing resin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper circuit patterns are used on ceramic insulating substrates, then electrical conductivity is improved, but thermal stress and peeling occur due to difference in linear expansion coefficients
Solution Approach 1:
The patent applies local quality by creating drill holes at specific locations around the copper blocks where thermal stress concentrates. The holes are positioned in the copper circuit patterns at the periphery of the copper blocks, making the stress relief measure localized rather than uniform throughout the entire circuit pattern. This targeted approach addresses the stress concentration problem at critical locations while maintaining electrical conductivity in other areas.
Solution Approach 2:
The patent introduces porosity by forming drill holes through the copper circuit patterns. These holes create a porous structure in the copper layer that allows for stress relief during thermal expansion and contraction cycles. The porous configuration reduces the average volume of the conductive film, thereby decreasing thermal stress concentration and preventing peeling between the sealing resin and substrate.
2Stress or pressure
If the average volume of conductive film is reduced by forming drill holes, then thermal stress is alleviated, but electrical conductivity may be affected
Solution Approach 1:
The drill holes are positioned specifically at the periphery of copper blocks where thermal stress concentrates, rather than uniformly distributing them throughout the entire copper circuit pattern. This localized placement ensures that electrical conductivity pathways through the copper blocks remain intact while stress relief is achieved at the critical interface regions between the copper blocks and sealing resin.
Solution Approach 2:
The patent applies partial action by forming drill holes only in specific regions of the copper circuit patterns - specifically around the periphery of copper blocks - rather than throughout the entire pattern. This partial application of hole formation is sufficient to relieve thermal stress at the critical interfaces without excessively compromising the overall electrical conductivity of the copper circuit network.
3Strength
If copper blocks are fixed to copper circuit patterns by diffusion bonding, then mechanical strength is improved, but stress concentration occurs at the bonded section
Solution Approach 1:
The drill holes are positioned at the periphery of copper blocks, creating a local quality change in the stress distribution. The holes are strategically placed where thermal stress concentrates during bonding and operation, providing localized stress relief at the bonded sections between copper blocks and copper circuit patterns, while maintaining the integrity of the bonded joints.
Solution Approach 2:
By forming drill holes around the copper blocks, the patent creates a porous structure that reduces thermal stress concentration at the bonded sections. The porous configuration allows for thermal expansion and contraction without generating excessive stress at the diffusion-bonded interfaces, thereby protecting the mechanical strength of the bonded joints between copper blocks, copper circuit patterns, and semiconductor chips.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces thermal stress concentration, enhances resin adhesion, and prevents peeling, thereby improving the reliability and lifespan of the semiconductor device by matching the linear expansion coefficients and providing an anchor effect for the resin.
Implementation Method 1
the difference in linear expansion coefficient between the insulating substrate made of ceramic and the copper circuit patterns
Implementation Method 2
a plurality of stress relaxation dimples are provided to the rim of a conductive pattern along the border between the ceramic substrate and the conductive pattern
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
The present invention provides a resin-sealed type semiconductor device capable of keeping the adhesive properties of sealing resin and improving the reliability and the like of the module. This resin-sealed type semiconductor device is a semiconductor device including: a conductive-patterned insulating substrate 1; conductive blocks 3a, 3b fixed to conductive patterns 2a, 2b of the conductive-patterned insulating substrate 1; a semiconductor chip 6 fixed to each conductive block; a printed circuit board 9 that has a conductive post 8 fixed to the semiconductor chip; and a resin 11 for sealing these constituents. The semiconductor device is configured such that the average volume of a conductive film per unit area of each conductive pattern around a section thereof, to which the corresponding conductive block is fixed, is reduced from the conductive block toward the outside.