Semiconductor Drive Circuit dV/dt Error Suppression
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Solution Overview
Problem
Existing semiconductor device drive circuits face instability and erroneous operations due to variations in secondary side reference potential (dV/dt), leading to unstable detection of dV/dt periods and oscillation in level shift circuits.
Innovation Solution
A semiconductor device drive circuit incorporating a pulse generation circuit, level shift circuits, dV/dt detection circuit, logic filter circuit, and impedance adjusting parts in pulse transmission circuits to reduce signal levels during dV/dt periods, preventing erroneous operations by stabilizing dV/dt detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the impedance of the level shift circuit is adjusted at the time of dV/dt to suppress error signals, then the error signal occurrence is reduced, but the dV/dt detection circuit cannot stably detect the dV/dt period and the output becomes unstable
Solution Approach 1:
The patent divides the signal processing into separate paths: one path (level shift circuit with impedance adjustment) handles error signal suppression, while another path (dV/dt detection circuit receiving original signals) handles detection. This segmentation allows both functions to operate independently without mutual interference, resolving the stability issue.
Solution Approach 2:
The patent introduces an intermediary mechanism where the dV/dt detection circuit receives the original input signals directly rather than the adjusted level shift output. This intermediary signal path ensures that detection stability is maintained while the level shift circuit performs impedance adjustment for error suppression.
2Adaptability or versatility
If feedback is applied from the impedance adjusting part to the dV/dt detection circuit, then impedance control is achieved, but the detection circuit receives feedback caused by drive of the impedance adjusting part
Solution Approach 1:
The patent extracts the dV/dt detection function from the impedance control feedback loop. The detection circuit receives original input signals directly, separating the detection function from the impedance adjustment feedback, thereby preventing information loss and detection inaccuracies.
3Reliability
If signal level is reduced during dV/dt period in pulse transmission circuits, then erroneous operation is prevented, but additional circuit complexity is introduced
Solution Approach 1:
The patent implements dynamic impedance adjustment in the pulse transmission circuits that is triggered by dV/dt detection. The impedance changing parts are activated only during dV/dt periods, providing adaptive error prevention without requiring permanently complex circuit structures. This dynamic approach balances reliability improvement with circuit simplicity.
Data Source
AI summary
An object of the present disclosure is to provide a semiconductor device drive circuit stably preventing an erroneous operation in accordance with an application of dV/dt. A semiconductor device drive circuit includes: pulse transmission circuits outputting an on-pulse transmission signal and an off-pulse transmission signal based on a level shift on-pulse signal and a level shift off-pulse signal; a dV/dt detection circuit detecting a dV/dt period based on the level shift on-pulse signal and the level shift off-pulse signal; a logic filter circuit which does not change outputs when both the on-pulse transmission signal and the off-pulse transmission signal are input; and a latch circuit outputting a signal synchronized with an output of the logic filter circuit. The pulse transmission circuit includes impedance adjusting parts reducing a signal level of the on-pulse transmission signal and the off-pulse transmission signal during the dV/dt period.