Semiconductor Drive Circuit Staged Gate Control
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Solution Overview
Problem
Voltage driven-type semiconductor devices face a trade-off between switching loss and short-circuit duration, where reducing switching loss increases collector current, thereby shortening the short-circuit duration, making it difficult to improve both simultaneously.
Innovation Solution
A driving method and circuit for semiconductor devices with multiple parallel-connected elements and insulated gate interconnections, where an ON-voltage is applied to all gate interconnections initially, and after a predetermined time, the OFF-voltage is applied to one interconnection while maintaining ON-voltage on another, optimizing current control to extend short-circuit duration without increasing switching loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If high electronic current is supplied during turn-on to reduce switching loss, then switching loss is reduced, but collector current increases which shortens the short-circuit duration
Solution Approach 1:
The gate control is segmented into multiple independent gate patterns (first gate pattern and second gate pattern) that can be controlled separately. This allows different portions of the semiconductor elements to be turned on at different times, enabling optimization of both switching loss and short-circuit duration through staged activation rather than simultaneous switching of all elements.
Solution Approach 2:
The first gate pattern is activated before the second gate pattern during turn-on. This preliminary action allows initial current flow through a subset of elements, establishing a controlled current profile that reduces switching loss while maintaining safety margins for short-circuit protection before full activation occurs.
2Duration of action of moving object
If collector current is suppressed to extend short-circuit duration, then short-circuit duration is increased, but switching loss increases due to reduced electronic current during turn-on
Solution Approach 1:
By dividing the gate control into separate patterns, the system can suppress current in some segments while maintaining full current in others, achieving an optimized balance between extending short-circuit duration and maintaining acceptable switching loss levels.
Solution Approach 2:
Different gate patterns are assigned different control characteristics - the first gate pattern allows higher current for switching performance, while the second gate pattern is controlled to extend short-circuit duration. This local differentiation of control quality across parallel elements resolves the global contradiction.
Data Source
AI summary
A semiconductor device includes a plurality of first transistor cells and a plurality of second transistor cells that are electrically connected in parallel between a collector electrode and an emitter electrode. A gate voltage on each of the plurality of first transistor cells is controlled by a first gate interconnection. A gate voltage on each of the plurality of second transistor cells is controlled by a second gate interconnection. A drive circuit is configured to: apply an ON-voltage of the semiconductor device to each of the first and second gate interconnections when the semiconductor device is turned on; and after a lapse of a predetermined time period since start of application of the ON-voltage, apply an OFF-voltage of the semiconductor device to the second gate interconnection and apply an ON-voltage to the first gate interconnection.